pga.lis

塞普拉思(sypress) 的ad转换应用范例.

 0050           DBB30FN:      equ 50h          ; Function Register                        (RW)
 0051           DBB30IN:      equ 51h          ;    Input Register                        (RW)
 0052           DBB30OU:      equ 52h          ;   Output Register                        (RW)
 0000           
 0000           ; Digital PSoC block 31, Basic Type B
 0054           DBB31FN:      equ 54h          ; Function Register                        (RW)
 0055           DBB31IN:      equ 55h          ;    Input Register                        (RW)
 0056           DBB31OU:      equ 56h          ;   Output Register                        (RW)
 0000           
 0000           ; Digital PSoC block 32, Communications Type B
 0058           DCB32FN:      equ 58h          ; Function Register                        (RW)
 0059           DCB32IN:      equ 59h          ;    Input Register                        (RW)
 005A           DCB32OU:      equ 5Ah          ;   Output Register                        (RW)
 0000           
 0000           ; Digital PSoC block 33, Communications Type B
 005C           DCB33FN:      equ 5Ch          ; Function Register                        (RW)
 005D           DCB33IN:      equ 5Dh          ;    Input Register                        (RW)
 005E           DCB33OU:      equ 5Eh          ;   Output Register                        (RW)
 0000           
 0000           ;------------------------------------------------
 0000           ;  System and Global Resource Registers
 0000           ;  Note: Also see this address range in Bank 0.
 0000           ;------------------------------------------------
 0000           
 0060           CLK_CR0:      equ 60h          ; Analog Column Clock Select Register 0    (RW)
 00C0           CLK_CR0_ACOLUMN_3:    equ 0C0h    ; MASK: Specify clock for analog cloumn
 0030           CLK_CR0_ACOLUMN_2:    equ 30h    ; MASK: Specify clock for analog cloumn
 000C           CLK_CR0_ACOLUMN_1:    equ 0Ch    ; MASK: Specify clock for analog cloumn
 0003           CLK_CR0_ACOLUMN_0:    equ 03h    ; MASK: Specify clock for analog cloumn
 0000           
 0061           CLK_CR1:      equ 61h          ; Analog Clock Source Select Register 1    (RW)
 0040           CLK_CR1_SHDIS:        equ 40h    ; MASK: Sample and Hold Disable (all Columns)
 0038           CLK_CR1_ACLK1:        equ 38h    ; MASK: Digital PSoC block for analog source
 0007           CLK_CR1_ACLK2:        equ 07h    ; MASK: Digital PSoC block for analog source
 0000           
 0062           ABF_CR0:      equ 62h          ; Analog Output Buffer Control Register 0  (RW)
 0080           ABF_CR0_ACOL1MUX:     equ 80h    ; MASK: Analog Column 1 Mux control
 0040           ABF_CR0_ACOL2MUX:     equ 40h    ; MASK: Analog Column 2 Mux control
 0020           ABF_CR0_ABUF1EN:      equ 20h    ; MASK: Enable ACol 1 analog buffer (P0[5])
 0010           ABF_CR0_ABUF2EN:      equ 10h    ; MASK: Enable ACol 2 analog buffer (P0[4])
 0008           ABF_CR0_ABUF0EN:      equ 08h    ; MASK: Enable ACol 0 analog buffer (P0[3])
 0004           ABF_CR0_ABUF3EN:      equ 04h    ; MASK: Enable ACol 3 analog buffer (P0[2])
 0002           ABF_CR0_BYPASS:       equ 02h    ; MASK: Bypass the analog buffers
 0001           ABF_CR0_PWR:          equ 01h    ; MASK: High power mode on all analog buffers
 0000           
 0063           AMD_CR0:      equ 63h          ; Analog Modulator Control Register 0      (RW)
 0070           AMD_CR0_AMOD2:        equ 70h    ; MASK: Modulation source for analog column 2
 0007           AMD_CR0_AMOD0:        equ 07h    ; MASK: Modulation source for analog column 1
 0000           
 0066           AMD_CR1:      equ 66h          ; Analog Modulator Control Register 1      (RW)
 0070           AMD_CR1_AMOD3:        equ 70h    ; MASK: Modulation ctrl for analog column 3
 0007           AMD_CR1_AMOD1:        equ 07h    ; MASK: Modulation ctrl for analog column 1
 0000           
 0067           ALT_CR0:      equ 67h          ; Analog Look Up Table (LUT) Register 0    (RW)
 00F0           ALT_CR0_LUT1:         equ 0F0h    ; MASK: Look up table 1 selection
 000F           ALT_CR0_LUT0:         equ 0Fh    ; MASK: Look up table 0 selection
 0000           
 0068           ALT_CR1:      equ 68h          ; Analog Look Up Table (LUT) Register 1    (RW)
 00F0           ALT_CR1_LUT3:         equ 0F0h    ; MASK: Look up table 3 selection
 000F           ALT_CR1_LUT2:         equ 0Fh    ; MASK: Look up table 2 selection
 0000           
 0069           CLK_CR2:      equ 69h          ; Analog Clock Source Control Register 2   (RW)
 0008           CLK_CR2_ACLK1R:       equ 08h    ; MASK: Analog Clock 1 selection range
 0001           CLK_CR2_ACLK0R:       equ 01h    ; MASK: Analog Clock 0 selection range
 0000           
 0000           ;------------------------------------------------
 0000           ;  Global Digital Interconnects
 0000           ;------------------------------------------------
 0000           
 00D0           GDI_O_IN:     equ 0D0h          ; Global Dig Interconnect Odd Inputs Reg   (RW)
 00D1           GDI_E_IN:     equ 0D1h          ; Global Dig Interconnect Even Inputs Reg  (RW)
 00D2           GDI_O_OU:     equ 0D2h          ; Global Dig Interconnect Odd Outputs Reg  (RW)
 00D3           GDI_E_OU:     equ 0D3h          ; Global Dig Interconnect Even Outputs Reg (RW)
 0000           
 0000           ;------------------------------------------------
 0000           ;  Clock and System Control Registers
 0000           ;------------------------------------------------
 0000           
 00DD           OSC_GO_EN:    equ 0DDh          ; Oscillator to Global Outputs Enable Register (RW)
 0080           OSC_GOEN_SLPINT:      equ 80h	 ; Enable Sleep Timer onto GOE[7]
 0040           OSC_GOEN_VC3:         equ 40h    ; Enable VC3 onto GOE[6]
 0020           OSC_GOEN_VC2:         equ 20h    ; Enable VC2 onto GOE[5]
 0010           OSC_GOEN_VC1:         equ 10h    ; Enable VC1 onto GOE[4]
 0008           OSC_GOEN_SYSCLKX2:    equ 08h    ; Enable 2X SysClk onto GOE[3]
 0004           OSC_GOEN_SYSCLK:      equ 04h    ; Enable 1X SysClk onto GOE[2]
 0002           OSC_GOEN_CLK24M:      equ 02h    ; Enable 24 MHz clock onto GOE[1]
 0001           OSC_GOEN_CLK32K:      equ 01h    ; Enable 32 kHz clock onto GOE[0]
 0000           
 00DE           OSC_CR4:      equ 0DEh          ; Oscillator Control Register 4            (RW)
 0003           OSC_CR4_VC3:          equ 03h    ; MASK: System VC3 Clock source
 0000           
 00DF           OSC_CR3:      equ 0DFh          ; Oscillator Control Register 3            (RW)
 0000           
 00E0           OSC_CR0:      equ 0E0h          ; System Oscillator Control Register 0     (RW)
 0080           OSC_CR0_32K_SELECT:   equ 80h    ; MASK: Enable/Disable External XTAL Osc
 0040           OSC_CR0_PLL_MODE:     equ 40h    ; MASK: Enable/Disable PLL
 0020           OSC_CR0_NO_BUZZ:      equ 20h    ; MASK: Bandgap always powered/BUZZ bandgap
 0018           OSC_CR0_SLEEP:        equ 18h    ; MASK: Set Sleep timer freq/period
 0000           OSC_CR0_SLEEP_512Hz:  equ 00h    ;     Set sleep bits for 1.95ms period
 0008           OSC_CR0_SLEEP_64Hz:   equ 08h    ;     Set sleep bits for 15.6ms period
 0010           OSC_CR0_SLEEP_8Hz:    equ 10h    ;     Set sleep bits for 125ms period
 0018           OSC_CR0_SLEEP_1Hz:    equ 18h    ;     Set sleep bits for 1 sec period
 0007           OSC_CR0_CPU:          equ 07h    ; MASK: Set CPU Frequency
 0000           OSC_CR0_CPU_3MHz:     equ 00h    ;     set CPU Freq bits for 3MHz Operation
 0001           OSC_CR0_CPU_6MHz:     equ 01h    ;     set CPU Freq bits for 6MHz Operation
 0002           OSC_CR0_CPU_12MHz:    equ 02h    ;     set CPU Freq bits for 12MHz Operation
 0003           OSC_CR0_CPU_24MHz:    equ 03h    ;     set CPU Freq bits for 24MHz Operation
 0004           OSC_CR0_CPU_1d5MHz:   equ 04h    ;     set CPU Freq bits for 1.5MHz Operation
 0005           OSC_CR0_CPU_750kHz:   equ 05h    ;     set CPU Freq bits for 750kHz Operation
 0006           OSC_CR0_CPU_187d5kHz: equ 06h    ;     set CPU Freq bits for 187.5kHz Operation
 0007           OSC_CR0_CPU_93d7kHz:  equ 07h    ;     set CPU Freq bits for 93.7kHz Operation
 0000           
 00E1           OSC_CR1:      equ 0E1h          ; System VC1/VC2 Divider Control Register  (RW)
 00F0           OSC_CR1_VC1:          equ 0F0h    ; MASK: System VC1 24MHz/External Clk divider
 000F           OSC_CR1_VC2:          equ 0Fh    ; MASK: System VC2 24MHz/External Clk divider
 0000           
 00E2           OSC_CR2:      equ 0E2h          ; Oscillator Control Register 2            (RW)
 0004           OSC_CR2_EXTCLKEN:     equ 04h    ; MASK: Enable/Disable External Clock
 0002           OSC_CR2_IMODIS:       equ 02h    ; MASK: Enable/Disable System (IMO) Clock Net
 0001           OSC_CR2_SYSCLKX2DIS:  equ 01h    ; MASK: Enable/Disable 48MHz clock source
 0000           
 00E3           VLT_CR:       equ 0E3h          ; Voltage Monitor Control Register         (RW)
 0080           VLT_CR_SMP:           equ 80h    ; MASK: Enable Switch Mode Pump
 0030           VLT_CR_PORLEV:        equ 30h    ; MASK: Mask for Power on Reset level control
 0000           VLT_CR_POR_LOW:       equ 00h    ;   Lowest  Precision Power-on Reset trip point
 0010           VLT_CR_POR_MID:       equ 10h    ;   Middle  Precision Power-on Reset trip point
 0020           VLT_CR_POR_HIGH:      equ 20h    ;   Highest Precision Power-on Reset trip point
 0008           VLT_CR_LVDTBEN:       equ 08h    ; MASK: Enable the CPU Throttle Back on LVD
 0007           VLT_CR_VM:            equ 07h    ; MASK: Mask for Voltage Monitor level setting
 0000           VLT_CR_3V0_POR:       equ 00h    ; -- deprecated symbols --
 0010           VLT_CR_4V5_POR:       equ 10h    ;    deprecated
 0020           VLT_CR_4V75_POR:      equ 20h    ;    deprecated
 0030           VLT_CR_DISABLE:       equ 30h    ;    deprecated
 0000           
 00E4           VLT_CMP:      equ 0E4h          ; Voltage Monitor Comparators Register     (R)
 0004           VLT_CMP_PUMP:         equ 04h    ; MASK: Vcc below SMP trip level
 0002           VLT_CMP_LVD:          equ 02h    ; MASK: Vcc below LVD trip level
 0001           VLT_CMP_PPOR:         equ 01h    ; MASK: Vcc below PPOR trip level
 0000           
 00E7           DEC_CR2:      equ 0E7h          ; Decimator Control Register 2             (RW)
 00E8           IMO_TR:       equ 0E8h          ; Internal Main Oscillator Trim Register   (W)
 00E9           ILO_TR:       equ 0E9h          ; Internal Low-speed Oscillator Trim       (W)
 00EA           BDG_TR:       equ 0EAh          ; Band Gap Trim Register                   (W)
 00EB           ECO_TR:       equ 0EBh          ; External Oscillator Trim Register        (W)
 0000           
 0000           ;;=============================================================================
 0000           ;;      M8C System Macros
 0000           ;;  These macros should be used when their functions are needed.
 0000           ;;=============================================================================
 0000           
 0000           ;----------------------------------------------------
 0000           ;  Swapping Register Banks
 0000           ;----------------------------------------------------
 0000               macro M8C_SetBank0
 0000               and   F, ~FLAG_XIO_MASK
 0000               macro M8C_SetBank1
 0000               or    F, FLAG_XIO_MASK
 0000               macro M8C_EnableGInt
 0000               or    F, FLAG_GLOBAL_IE
 0000               macro M8C_DisableGInt
 0000               and   F, ~FLAG_GLOBAL_IE
 0000               macro M8C_DisableIntMask
 0000               and   reg[@0], ~@1              ; disable specified interrupt enable bit
 0000               macro M8C_EnableIntMask
 0000               or    reg[@0], @1               ; enable specified interrupt enable bit
 0000               macro M8C_ClearIntFlag
 0000               mov   reg[@0], ~@1              ; clear specified interrupt enable bit
 0000               macro M8C_EnableWatchDog
 0000               and   reg[CPU_SCR0], ~CPU_SCR0_PORS_MASK
 0000               macro M8C_ClearWDT
 0000               mov   reg[RES_WDT], 00h
 0000               macro M8C_ClearWDTAndSleep
 0000               mov   reg[RES_WDT], 38h
 0000               macro M8C_Stall
 0000               or    reg[ASY_CR], ASY_CR_SYNCEN
 0000               macro M8C_Unstall
 0000               and   reg[ASY_CR], ~ASY_CR_S