📄 pga.lis
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0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000 ;; FILENAME: PGA.asm ( PGA )
0000 ;; Version: 3.2, Updated on 2006/01/14 at 16:06:54
0000 ;; Generated by PSoC Designer ver 4.4 b1884 : 14 Jan, 2007
0000 ;;
0000 ;; DESCRIPTION: PGA User Module software implementation file for the
0000 ;; 22/24/27/29xxx PSoC family of devices.
0000 ;;
0000 ;; NOTE: User Module APIs conform to the fastcall16 convention for marshalling
0000 ;; arguments and observe the associated "Registers are volatile" policy.
0000 ;; This means it is the caller's responsibility to preserve any values
0000 ;; in the X and A registers that are still needed after the API functions
0000 ;; returns. For Large Memory Model devices it is also the caller's
0000 ;; responsibility to perserve any value in the CUR_PP, IDX_PP, MVR_PP and
0000 ;; MVW_PP registers. Even though some of these registers may not be modified
0000 ;; now, there is no guarantee that will remain the case in future releases.
0000 ;;-----------------------------------------------------------------------------
0000 ;; Copyright (c) Cypress MicroSystems 2004. All Rights Reserved.
0000 ;;*****************************************************************************
0000 ;;*****************************************************************************
0000
0000 ;; -----------------------------------------------------------------
0000 ;; Register Definitions
0000 ;;
0000 ;; Uses 1 Continuous Time Block configured as shown.
0000 ;;
0000 ;; * For a Mask/Val pair, this indicates that the value is
0000 ;; determined by the user either through config-time parameteriza-
0000 ;; tion or run-time manipulation.
0000 ;;
0000 ;; BIT FIELD Mask/Val Function
0000 ;; ----------------- ----- --------------------
0000 ;; GAIN_CR0.RES_RATIO_T2B F0/* User Parameter (by table)
0000 ;; GAIN_CR0.GAIN_ATTEN 08/* Gain (by table)
0000 ;; GAIN_CR0.RES_SOURCE 04/1 Res source to output
0000 ;; GAIN_CR0.RES_REF 03/* Res ref
0000 ;;
0000 ;; GAIN_CR1.A_OUT 80/* User Parameter (Output bus)
0000 ;; GAIN_CR1.COMP_EN 40/0 Comparator bus disabled
0000 ;; GAIN_CR1.CT_NEG_INPUT_MUX 38/4 Neg mux to analog f.b. tap
0000 ;; GAIN_CR1.CT_POS_INPUT_MUX 07/* Pos mux, typically to col. input mux
0000 ;;
0000 ;; GAIN_CR2.CP_COMP 80/0 Latch transparent on PH1
0000 ;; GAIN_CR2.CK_COMP 40/0 Latch transparent
0000 ;; GAIN_CR2.CC_COMP 20/1 Mode OP-AMP (not comparator)
0000 ;; GAIN_CR2.BYPASS_OBUS 1C/0 Bypass OFF
0000 ;; GAIN_CR2.PWR_SELECT 03/* Power OFF (0h) at start-up
0000 ;;
0000 ;; --------------------------------------------------------------------
0000
0000 PGA_OFF: equ 0
0001 PGA_LOWPOWER: equ 1
0002 PGA_MEDPOWER: equ 2
0003 PGA_HIGHPOWER: equ 3
0000
000C PGA_G48_0: equ 0Ch
001C PGA_G24_0: equ 1Ch
0008 PGA_G16_0: equ 08h
0018 PGA_G8_00: equ 18h
0028 PGA_G5_33: equ 28h
0038 PGA_G4_00: equ 38h
0048 PGA_G3_20: equ 48h
0058 PGA_G2_67: equ 58h
0068 PGA_G2_27: equ 68h
0078 PGA_G2_00: equ 78h
0088 PGA_G1_78: equ 88h
0098 PGA_G1_60: equ 98h
00A8 PGA_G1_46: equ A8h
00B8 PGA_G1_33: equ B8h
00C8 PGA_G1_23: equ C8h
00D8 PGA_G1_14: equ D8h
00E8 PGA_G1_06: equ E8h
00F8 PGA_G1_00: equ F8h
00E0 PGA_G0_93: equ E0h
00D0 PGA_G0_87: equ D0h
00C0 PGA_G0_81: equ C0h
00B0 PGA_G0_75: equ B0h
00A0 PGA_G0_68: equ A0h
0090 PGA_G0_62: equ 90h
0080 PGA_G0_56: equ 80h
0070 PGA_G0_50: equ 70h
0060 PGA_G0_43: equ 60h
0050 PGA_G0_37: equ 50h
0040 PGA_G0_31: equ 40h
0030 PGA_G0_25: equ 30h
0020 PGA_G0_18: equ 20h
0010 PGA_G0_12: equ 10h
0000 PGA_G0_06: equ 00h
0000
0000
0000 ;--------------------------------------------------
0000 ; Register Address Constants used by PGA
0000 ;--------------------------------------------------
0071 PGA_GAIN_CR0: equ 71h
0072 PGA_GAIN_CR1: equ 72h
0073 PGA_GAIN_CR2: equ 73h
0070 PGA_GAIN_CR3: equ 70h
0000
00C0 FLAG_PGMODE_MASK: equ 0C0h ; Paging control for > 256 bytes of RAM
0000 FLAG_PGMODE_0: equ 00h ; Direct to Page 0, indexed to Page 0
0040 FLAG_PGMODE_1: equ 40h ; Direct to Page 0, indexed to STK_PP page
0080 FLAG_PGMODE_2: equ 80h ; Direct to CUR_PP page, indexed to IDX_PP page
00C0 FLAG_PGMODE_3: equ 0C0h ; Direct to CUR_PP page, indexed to STK_PP page
0000 FLAG_PGMODE_00b: equ 00h ; Same as PGMODE_0
0040 FLAG_PGMODE_01b: equ 40h ; Same as PGMODE_1
0080 FLAG_PGMODE_10b: equ 80h ; Same as PGMODE_2
00C0 FLAG_PGMODE_11b: equ 0C0h ; Same as PGMODE_3
0010 FLAG_XIO_MASK: equ 10h ; I/O Bank select for register space
0008 FLAG_SUPER: equ 08h ; Supervisor Mode
0004 FLAG_CARRY: equ 04h ; Carry Condition Flag
0002 FLAG_ZERO: equ 02h ; Zero Condition Flag
0001 FLAG_GLOBAL_IE: equ 01h ; Glogal Interrupt Enable
0000
0000
0000 ;;=============================================================================
0000 ;; Register Space, Bank 0
0000 ;;=============================================================================
0000
0000 ;------------------------------------------------
0000 ; Port Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Port 0
0000 PRT0DR: equ 00h ; Port 0 Data Register (RW)
0001 PRT0IE: equ 01h ; Port 0 Interrupt Enable Register (RW)
0002 PRT0GS: equ 02h ; Port 0 Global Select Register (RW)
0003 PRT0DM2: equ 03h ; Port 0 Drive Mode 2 (RW)
0000 ; Port 1
0004 PRT1DR: equ 04h ; Port 1 Data Register (RW)
0005 PRT1IE: equ 05h ; Port 1 Interrupt Enable Register (RW)
0006 PRT1GS: equ 06h ; Port 1 Global Select Register (RW)
0007 PRT1DM2: equ 07h ; Port 1 Drive Mode 2 (RW)
0000 ; Port 2
0008 PRT2DR: equ 08h ; Port 2 Data Register (RW)
0009 PRT2IE: equ 09h ; Port 2 Interrupt Enable Register (RW)
000A PRT2GS: equ 0Ah ; Port 2 Global Select Register (RW)
000B PRT2DM2: equ 0Bh ; Port 2 Drive Mode 2 (RW)
0000 ; Port 3
000C PRT3DR: equ 0Ch ; Port 3 Data Register (RW)
000D PRT3IE: equ 0Dh ; Port 3 Interrupt Enable Register (RW)
000E PRT3GS: equ 0Eh ; Port 3 Global Select Register (RW)
000F PRT3DM2: equ 0Fh ; Port 3 Drive Mode 2 (RW)
0000 ; Port 4
0010 PRT4DR: equ 10h ; Port 4 Data Register (RW)
0011 PRT4IE: equ 11h ; Port 4 Interrupt Enable Register (RW)
0012 PRT4GS: equ 12h ; Port 4 Global Select Register (RW)
0013 PRT4DM2: equ 13h ; Port 4 Drive Mode 2 (RW)
0000 ; Port 5
0014 PRT5DR: equ 14h ; Port 5 Data Register (RW)
0015 PRT5IE: equ 15h ; Port 5 Interrupt Enable Register (RW)
0016 PRT5GS: equ 16h ; Port 5 Global Select Register (RW)
0017 PRT5DM2: equ 17h ; Port 5 Drive Mode 2 (RW)
0000 ; Port 6
0018 PRT6DR: equ 18h ; Port 6 Data Register (RW)
0019 PRT6IE: equ 19h ; Port 6 Interrupt Enable Register (RW)
001A PRT6GS: equ 1Ah ; Port 6 Global Select Register (RW)
001B PRT6DM2: equ 1Bh ; Port 6 Drive Mode 2 (RW)
0000 ; Port 7
001C PRT7DR: equ 1Ch ; Port 7 Data Register (RW)
001D PRT7IE: equ 1Dh ; Port 7 Interrupt Enable Register (RW)
001E PRT7GS: equ 1Eh ; Port 7 Global Select Register (RW)
001F PRT7DM2: equ 1Fh ; Port 7 Drive Mode 2 (RW)
0000
0000 ;------------------------------------------------
0000 ; Digital PSoC(tm) block Registers
0000 ; Note: Also see this address range in Bank 1.
0000 ;------------------------------------------------
0000 ; Digital PSoC block 00, Basic Type B
0020 DBB00DR0: equ 20h ; data register 0 (#)
0021 DBB00DR1: equ 21h ; data register 1 (W)
0022 DBB00DR2: equ 22h ; data register 2 (RW)
0023 DBB00CR0: equ 23h ; control & status register 0 (#)
0000
0000 ; Digital PSoC block 01, Basic Type B
0024 DBB01DR0: equ 24h ; data register 0 (#)
0025 DBB01DR1: equ 25h ; data register 1 (W)
0026 DBB01DR2: equ 26h ; data register 2 (RW)
0027 DBB01CR0: equ 27h ; control & status register 0 (#)
0000
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