bin_bcd_lcd.v

具有LCD显示单元的可编程单脉冲发生器的硬件实现

module  BIN_BCD_LCD (CLK_40Mhz, CLR, A, PH, P, DP, LD); 
    input    CLK_40Mhz, CLR; 
    input     [16:0] A;
    output   PH;                   
    output   [3:0] DP;              
    output   [4:0] LD;              
    output   [3:0] P;                
        
    wire     CLK_1Khz;  
    wire     [3:0] BW, BQ, BB, BS, BG;


    CNT  CNT  (CLK_40Mhz, CLK_1Khz); 

    BIN_BCD   BIN_BCD  (CLK_1Khz, A, BW, BQ, BB, BS, BG);

    LCD   LCD (CLK_1Khz, CLR, BW, BQ, BB, BS, BG, PH, P, DP, LD);

endmodule

/**********分频模块 ***********/
module	CNT (CLK, DIV_CLK);  
    input	CLK;           
    reg 	[15:0] Q;   
    output	DIV_CLK;          
  
    always @(posedge CLK)       
      begin   
        if (Q==39999)                
            Q<=0;                  
         else 
            Q<=Q+1;    
      end           

    assign  DIV_CLK=~Q[15];        
endmodule

/**********LCD显示模块***********/
module  LCD (CLK, CLR, NUMW, NUMQ, NUMB, NUMS, NUMG, PH, P, DP, LD);
    input    CLK, CLR;
    input    [3:0] NUMW, NUMQ, NUMB, NUMS, NUMG;
    output   PH;
    output   [3:0] DP;
    output   [4:0] LD;
    output   [3:0] P;
    reg      [4:0] LD;
    reg      [3:0] P;
    reg      [2:0]COUNT;

    assign  PH=CLK;
    assign  DP[3]=CLK; 
    assign  DP[2]=CLK; 
    assign  DP[1]=CLK; 
    assign  DP[0]=CLK; 
                 
  
    always @ (posedge CLK or negedge CLR)
         if (!CLR)
            COUNT<=0;
         else if (COUNT==5)
            COUNT<=1;
         else 
            COUNT<=COUNT+1;
    
    
    always @ (COUNT)
      begin
         case (COUNT)
           3'b001:begin
                     P=NUMW;
                     LD=5'b00001;
                  end
           3'b010:begin
                     P=NUMQ;
                     LD=5'b00010;
                  end
           3'b011:begin
                     P=NUMB;
                     LD=5'b00100;
                  end
           3'b100:begin
                     P=NUMS;
                     LD=5'b01000;
                  end
           3'b101:begin
                     P=NUMG;
                     LD=5'b10000;
                  end
        endcase           
     end
endmodule


/*************二进制数转换BCD码模块******************/						
module BIN_BCD (CLK, A, BW, BQ, BB, BS, BG);		
    input CLK;
    input  [16:0]A;        
    output [3:0]BW, BQ, BB, BS, BG;        	
    reg    [3:0]BW, BQ, BB, BS, BG;      
  					
    integer I;
    reg  [19:0]TEMP;
    reg  [16:0]C;
						
    					
    always @ (posedge CLK)
     begin
       C=A;
       TEMP=0;

       for (I=1; I<17; I=I+1)
           begin
           {TEMP, C}={TEMP[18:0], C, 1'b0};
           if (TEMP[3:0]>4'b0100)
              begin
                TEMP[3:0]=TEMP[3:0]+3;
              end 
           if (TEMP[7:4]>4'b0100)
              begin
                TEMP[7:4]=TEMP[7:4]+3;
              end 
           if (TEMP[11:8]>4'b0100)
              begin
                TEMP[11:8]=TEMP[11:8]+3;
              end 
           if (TEMP[15:12]>4'b0100)
              begin
                TEMP[15:12]=TEMP[15:12]+3;
              end 
           if (TEMP[19:16]>4'b0100)
              begin
                TEMP[19:16]=TEMP[19:16]+3;
              end 
           {BW, BQ, BB,  BS, BG}={TEMP[18:0], A[0]};
           end
     end
  
endmodule