pxadma.cod

来自「这是mobile6.0下的DMB驱动」· COD 代码 · 共 537 行 · 第 1/2 页

  00000		 |PhyDmaSendDescriptor| PROC

; 88   : {

  00000		 |$L39041|
  00000	e92d4070	 stmdb       sp!, {r4 - r6, lr}
  00004	e24dd004	 sub         sp, sp, #4
  00008		 |$M39039|
  00008	e1a03001	 mov         r3, r1
  0000c	e1a05000	 mov         r5, r0

; 89   : 	volatile DMAC_REGISTERS_P	pDmacAddr;
; 90   : 	DWORD						tmp;
; 91   : 	DMAC_FRAME_DESCRIPTOR_ST*	desc;
; 92   : 	DMA_DESCRIPTOR_ST*			dbDesc = transaction->desc;
; 93   : 
; 94   : 	ResetEvent(dev->dmaIntEvent);

  00010	e595000c	 ldr         r0, [r5, #0xC]
  00014	e5936000	 ldr         r6, [r3]
  00018	e3a01002	 mov         r1, #2
  0001c	eb000000	 bl          EventModify

; 95   : 	pDmacAddr = dev->pDmacAddr;
; 96   : 
; 97   : 	desc = dev->desc;

  00020	e5954038	 ldr         r4, [r5, #0x38]

; 98   : 
; 99   : 	desc->ddadr = 1;

  00024	e5952000	 ldr         r2, [r5]
  00028	e3a03001	 mov         r3, #1
  0002c	e5843000	 str         r3, [r4]

; 100  : 	desc->dsadr = dbDesc->srcPhyAddr;

  00030	e5963000	 ldr         r3, [r6]

; 101  : 	desc->dtadr = dbDesc->dstPhyAddr;
; 102  : 	desc->dcmd = dbDesc->len;
; 103  : 
; 104  : 	tmp = userBurstSizeToDmaConfig[dev->burstSize];
; 105  : 	desc->dcmd |= (tmp<<16);								// BURST

  00034	e58d2000	 str         r2, [sp]
  00038	e59fe12c	 ldr         lr, [pc, #0x12C]
  0003c	e5843004	 str         r3, [r4, #4]
  00040	e5963004	 ldr         r3, [r6, #4]
  00044	e28e100c	 add         r1, lr, #0xC
  00048	e5843008	 str         r3, [r4, #8]
  0004c	e5962008	 ldr         r2, [r6, #8]
  00050	e584200c	 str         r2, [r4, #0xC]
  00054	e5953014	 ldr         r3, [r5, #0x14]
  00058	e7913103	 ldr         r3, [r1, +r3, lsl #2]
  0005c	e1822803	 orr         r2, r2, r3, lsl #16
  00060	e584200c	 str         r2, [r4, #0xC]

; 106  : 	tmp = userBusWidthToDmaConfig[dev->busWidth];
; 107  : 	desc->dcmd |= (tmp<<14);								// TRANSFER WIDTH	

  00064	e5953018	 ldr         r3, [r5, #0x18]
  00068	e79e3103	 ldr         r3, [lr, +r3, lsl #2]
  0006c	e1822703	 orr         r2, r2, r3, lsl #14
  00070	e584200c	 str         r2, [r4, #0xC]

; 108  : 
; 109  : 	if (dbDesc->flags & DMA_INC_SRC_ADDR)

  00074	e596300c	 ldr         r3, [r6, #0xC]
  00078	e3130001	 tst         r3, #1

; 110  : 		desc->dcmd |= DMAC_DCMD_INCSRCADDR;

  0007c	13823102	 orrne       r3, r2, #2, 2
  00080	1584300c	 strne       r3, [r4, #0xC]

; 111  : 	if (dbDesc->flags & DMA_INC_DST_ADDR)

  00084	e596300c	 ldr         r3, [r6, #0xC]
  00088	e3130002	 tst         r3, #2

; 112  : 		desc->dcmd |= DMAC_DCMD_INCTRGADDR;

  0008c	1594300c	 ldrne       r3, [r4, #0xC]
  00090	13833101	 orrne       r3, r3, #1, 2
  00094	1584300c	 strne       r3, [r4, #0xC]

; 113  : 
; 114  : 	if (dbDesc->flags & DMA_USE_DST_FLOW_CONTROL)

  00098	e596300c	 ldr         r3, [r6, #0xC]
  0009c	e3130004	 tst         r3, #4

; 115  : 		desc->dcmd |= DMAC_DCMD_FLOWTRG;

  000a0	1594300c	 ldrne       r3, [r4, #0xC]
  000a4	13833201	 orrne       r3, r3, #1, 4
  000a8	1584300c	 strne       r3, [r4, #0xC]

; 116  : 	if (dbDesc->flags & DMA_USE_SRC_FLOW_CONTROL)

  000ac	e596300c	 ldr         r3, [r6, #0xC]
  000b0	e3130008	 tst         r3, #8

; 117  : 		desc->dcmd |= DMAC_DCMD_FLOWSRC;

  000b4	1594300c	 ldrne       r3, [r4, #0xC]
  000b8	13833202	 orrne       r3, r3, #2, 4
  000bc	1584300c	 strne       r3, [r4, #0xC]

; 118  : 
; 119  : 
; 120  : 	desc->dcmd |= DMAC_DCMD_ENDIRQEN;						// Enable end interrupt for last descriptor.

  000c0	e594300c	 ldr         r3, [r4, #0xC]
  000c4	e3833602	 orr         r3, r3, #2, 12
  000c8	e584300c	 str         r3, [r4, #0xC]

; 121  : 
; 122  :     if (dev->useHWFlowCtrl == TRUE)

  000cc	e595301c	 ldr         r3, [r5, #0x1C]
  000d0	e3530001	 cmp         r3, #1

; 123  :     {//Request to Channel Map for DREQ 
; 124  :         pDmacAddr->drcmr1[dev->dmaReq] = DMAC_DRCRM_MAP_CHANNEL + dev->channel;

  000d4	05952004	 ldreq       r2, [r5, #4]
  000d8	05951010	 ldreq       r1, [r5, #0x10]
  000dc	059d3000	 ldreq       r3, [sp]
  000e0	02822080	 addeq       r2, r2, #0x80
  000e4	00833101	 addeq       r3, r3, r1, lsl #2
  000e8	05832100	 streq       r2, [r3, #0x100]

; 125  :     }
; 126  : 
; 127  : 
; 128  : 	//Clear all existing interrupts and set mode to no descriptor fetch
; 129  : 	pDmacAddr->dcsr[dev->channel] = DMAC_DCSR_CLEAR_ALL_INTERRUPTS;		

  000ec	e5952004	 ldr         r2, [r5, #4]
  000f0	e59d3000	 ldr         r3, [sp]
  000f4	e3a0101f	 mov         r1, #0x1F
  000f8	e7831102	 str         r1, [r3, +r2, lsl #2]

; 130  : 	
; 131  : 
; 132  : 	// DALGN - DMA ALIGNMENT REG.
; 133  : 	if ((dbDesc[0].srcPhyAddr & 0x7) || (dbDesc[0].dstPhyAddr & 7))

  000fc	e5963000	 ldr         r3, [r6]
  00100	e3130007	 tst         r3, #7
  00104	05963004	 ldreq       r3, [r6, #4]
  00108	03130007	 tsteq       r3, #7

; 134  : 		pDmacAddr->dalgn |= 1<<dev->channel;
; 135  : 	else
; 136  : 		pDmacAddr->dalgn &= ~(1<<dev->channel);

  0010c	059d1000	 ldreq       r1, [sp]
  00110	05952004	 ldreq       r2, [r5, #4]
  00114	03a00001	 moveq       r0, #1
  00118	05b130a0	 ldreq       r3, [r1, #0xA0]!
  0011c	159d1000	 ldrne       r1, [sp]
  00120	01c33210	 biceq       r3, r3, r0, lsl r2
  00124	15b130a0	 ldrne       r3, [r1, #0xA0]!
  00128	15952004	 ldrne       r2, [r5, #4]
  0012c	13a00001	 movne       r0, #1
  00130	11833210	 orrne       r3, r3, r0, lsl r2
  00134	e5813000	 str         r3, [r1]

; 137  : 	
; 138  : 	//Set DMA first descriptor
; 139  : 	pDmacAddr->ddg[dev->channel].ddadr = dev->descPhyAddr.LowPart;

  00138	e59d3000	 ldr         r3, [sp]

; 140  : 	
; 141  : 	// Start Running
; 142  : 	pDmacAddr->dcsr[dev->channel] = DMAC_DCSR_RUN;// | DMAC_DCSR_EORIRQEN;

  0013c	e59de000	 ldr         lr, [sp]
  00140	e5951004	 ldr         r1, [r5, #4]
  00144	e5952030	 ldr         r2, [r5, #0x30]
  00148	e0833201	 add         r3, r3, r1, lsl #4
  0014c	e5832200	 str         r2, [r3, #0x200]
  00150	e5953004	 ldr         r3, [r5, #4]
  00154	e3a02102	 mov         r2, #2, 2

; 143  : 
; 144  : 
; 145  : 	return TRUE;

  00158	e3a00001	 mov         r0, #1
  0015c	e78e2103	 str         r2, [lr, +r3, lsl #2]

; 146  : }

  00160	e28dd004	 add         sp, sp, #4
  00164	e8bd4070	 ldmia       sp!, {r4 - r6, lr}
  00168	e12fff1e	 bx          lr
  0016c		 |$L39044|
  0016c	00000000	 DCD         |userBusWidthToDmaConfig|
  00170		 |$M39040|

			 ENDP  ; |PhyDmaSendDescriptor|

	EXPORT	|PhyDmaIntHandler|
	IMPORT	|GetEventData|

  00000			 AREA	 |.text| { |PhyDmaIntHandler| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000			 AREA	 |.pdata$$PhyDmaIntHandler|, PDATA, SELECTION=5, ASSOC=|.text| { |PhyDmaIntHandler| } ; comdat associative
|$T39054| DCD	|$L39053|
	DCD	0x40000a01
; Function compile flags: /Ogsy

  00000			 AREA	 |.text| { |PhyDmaIntHandler| }, CODE, ARM, SELECTION=1 ; comdat noduplicate

  00000		 |PhyDmaIntHandler| PROC

; 149  : {

  00000		 |$L39053|
  00000	e52de004	 str         lr, [sp, #-4]!
  00004		 |$M39051|

; 150  : 	DWORD stReg;
; 151  : 
; 152  : 	stReg = GetEventData(dev->dmaIntEvent);	

  00004	e590000c	 ldr         r0, [r0, #0xC]
  00008	eb000000	 bl          GetEventData

; 153  : 	//RETAILMSG(1, (TEXT("DMB dma int.\r\n")));
; 154  : 
; 155  : 	//Check that status returned from DMA controllers is good.
; 156  : 	if (stReg & DMAC_DCSR_ENDINTR || stReg & DMAC_DCSR_EORINT)	

  0000c	e3100004	 tst         r0, #4
  00010	03100c02	 tsteq       r0, #2, 24

; 158  : 	else
; 159  : 		return DMA_STATUS_ERR;

  00014	03e00000	 mvneq       r0, #0

; 160  : }

  00018	049de004	 ldreq       lr, [sp], #4

; 157  : 		return DMA_STATUS_OK;

  0001c	13a00000	 movne       r0, #0

; 160  : }

  00020	149de004	 ldrne       lr, [sp], #4
  00024	e12fff1e	 bx          lr
  00028		 |$M39052|

			 ENDP  ; |PhyDmaIntHandler|

	END