📄 ohci1394.h
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/* * ohci1394.h - driver for OHCI 1394 boards * Copyright (C)1999,2000 Sebastien Rougeaux <sebastien.rougeaux@anu.edu.au> * Gord Peters <GordPeters@smarttech.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software Foundation, * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */#ifndef _OHCI1394_H#define _OHCI1394_H#include "ieee1394_types.h"#include <asm/io.h>#define OHCI1394_DRIVER_NAME "ohci1394"#define OHCI1394_MAX_AT_REQ_RETRIES 0x2#define OHCI1394_MAX_AT_RESP_RETRIES 0x2#define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8#define OHCI1394_MAX_SELF_ID_ERRORS 16#define AR_REQ_NUM_DESC 4 /* number of AR req descriptors */#define AR_REQ_BUF_SIZE PAGE_SIZE /* size of AR req buffers */#define AR_REQ_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */#define AR_RESP_NUM_DESC 4 /* number of AR resp descriptors */#define AR_RESP_BUF_SIZE PAGE_SIZE /* size of AR resp buffers */#define AR_RESP_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */#define IR_NUM_DESC 16 /* number of IR descriptors */#define IR_BUF_SIZE PAGE_SIZE /* 4096 bytes/buffer */#define IR_SPLIT_BUF_SIZE PAGE_SIZE /* split packet buffer */#define IT_NUM_DESC 16 /* number of IT descriptors */#define AT_REQ_NUM_DESC 32 /* number of AT req descriptors */#define AT_RESP_NUM_DESC 32 /* number of AT resp descriptors */#define OHCI_LOOP_COUNT 100 /* Number of loops for reg read waits */#define OHCI_CONFIG_ROM_LEN 1024 /* Length of the mapped configrom space */#define OHCI1394_SI_DMA_BUF_SIZE 8192 /* length of the selfid buffer *//* PCI configuration space addresses */#define OHCI1394_PCI_HCI_Control 0x40struct dma_cmd { u32 control; u32 address; u32 branchAddress; u32 status;};/* * FIXME: * It is important that a single at_dma_prg does not cross a page boundary * The proper way to do it would be to do the check dynamically as the * programs are inserted into the AT fifo. */struct at_dma_prg { struct dma_cmd begin; quadlet_t data[4]; struct dma_cmd end; quadlet_t pad[4]; /* FIXME: quick hack for memory alignment */};/* identify whether a DMA context is asynchronous or isochronous */enum context_type { DMA_CTX_ASYNC_REQ, DMA_CTX_ASYNC_RESP, DMA_CTX_ISO };/* DMA receive context */struct dma_rcv_ctx { struct ti_ohci *ohci; enum context_type type; int ctx; unsigned int num_desc; unsigned int buf_size; unsigned int split_buf_size; /* dma block descriptors */ struct dma_cmd **prg_cpu; dma_addr_t *prg_bus; struct pci_pool *prg_pool; /* dma buffers */ quadlet_t **buf_cpu; dma_addr_t *buf_bus; unsigned int buf_ind; unsigned int buf_offset; quadlet_t *spb; spinlock_t lock; struct tasklet_struct task; int ctrlClear; int ctrlSet; int cmdPtr; int ctxtMatch;};/* DMA transmit context */struct dma_trm_ctx { struct ti_ohci *ohci; enum context_type type; int ctx; unsigned int num_desc; /* dma block descriptors */ struct at_dma_prg **prg_cpu; dma_addr_t *prg_bus; struct pci_pool *prg_pool; unsigned int prg_ind; unsigned int sent_ind; int free_prgs; quadlet_t *branchAddrPtr; /* list of packets inserted in the AT FIFO */ struct list_head fifo_list; /* list of pending packets to be inserted in the AT FIFO */ struct list_head pending_list; spinlock_t lock; struct tasklet_struct task; int ctrlClear; int ctrlSet; int cmdPtr;};struct ohci1394_iso_tasklet { struct tasklet_struct tasklet; struct list_head link; int context; enum { OHCI_ISO_TRANSMIT, OHCI_ISO_RECEIVE, OHCI_ISO_MULTICHANNEL_RECEIVE } type;};struct ti_ohci { struct pci_dev *dev; enum { OHCI_INIT_ALLOC_HOST, OHCI_INIT_HAVE_MEM_REGION, OHCI_INIT_HAVE_IOMAPPING, OHCI_INIT_HAVE_CONFIG_ROM_BUFFER, OHCI_INIT_HAVE_SELFID_BUFFER, OHCI_INIT_HAVE_TXRX_BUFFERS__MAYBE, OHCI_INIT_HAVE_IRQ, OHCI_INIT_DONE, } init_state; /* remapped memory spaces */ void __iomem *registers; /* dma buffer for self-id packets */ quadlet_t *selfid_buf_cpu; dma_addr_t selfid_buf_bus; /* buffer for csr config rom */ quadlet_t *csr_config_rom_cpu; dma_addr_t csr_config_rom_bus; int csr_config_rom_length; unsigned int max_packet_size; /* async receive */ struct dma_rcv_ctx ar_resp_context; struct dma_rcv_ctx ar_req_context; /* async transmit */ struct dma_trm_ctx at_resp_context; struct dma_trm_ctx at_req_context; /* iso receive */ int nb_iso_rcv_ctx; unsigned long ir_ctx_usage; /* use test_and_set_bit() for atomicity */ unsigned long ir_multichannel_used; /* ditto */ spinlock_t IR_channel_lock; /* iso receive (legacy API) */ u64 ir_legacy_channels; /* note: this differs from ISO_channel_usage; it only accounts for channels listened to by the legacy API, so that we can know when it is safe to free the legacy API context */ struct dma_rcv_ctx ir_legacy_context; struct ohci1394_iso_tasklet ir_legacy_tasklet; /* iso transmit */ int nb_iso_xmit_ctx; unsigned long it_ctx_usage; /* use test_and_set_bit() for atomicity */ /* iso transmit (legacy API) */ struct dma_trm_ctx it_legacy_context; struct ohci1394_iso_tasklet it_legacy_tasklet; u64 ISO_channel_usage; /* IEEE-1394 part follows */ struct hpsb_host *host; int phyid, isroot; spinlock_t phy_reg_lock; spinlock_t event_lock; int self_id_errors; /* Tasklets for iso receive and transmit, used by video1394 * and dv1394 */ struct list_head iso_tasklet_list; spinlock_t iso_tasklet_list_lock; /* Swap the selfid buffer? */ unsigned int selfid_swap:1; /* Some Apple chipset seem to swap incoming headers for us */ unsigned int no_swap_incoming:1; /* Force extra paranoia checking on bus-reset handling */ unsigned int check_busreset:1;};
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