📄 main.lst
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132 =2 sfr PCA0CPH0 = 0xFA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - HIGH BYTE */
133 =2 sfr PCA0CPH1 = 0xFB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - HIGH BYTE */
134 =2 sfr PCA0CPH2 = 0xFC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - HIGH BYTE */
135 =2 sfr PCA0CPH3 = 0xFD; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - HIGH BYTE */
136 =2 sfr PCA0CPH4 = 0xFE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - HIGH BYTE */
137 =2 sfr WDTCN = 0xFF; /* WATCHDOG TIMER CONTROL */
138 =2
139 =2
140 =2 /* BIT Registers */
141 =2
142 =2 /* TCON 0x88 */
143 =2 sbit TF1 = TCON ^ 7; /* TIMER 1 OVERFLOW FLAG */
144 =2 sbit TR1 = TCON ^ 6; /* TIMER 1 ON/OFF CONTROL */
145 =2 sbit TF0 = TCON ^ 5; /* TIMER 0 OVERFLOW FLAG */
146 =2 sbit TR0 = TCON ^ 4; /* TIMER 0 ON/OFF CONTROL */
147 =2 sbit IE1 = TCON ^ 3; /* EXT. INTERRUPT 1 EDGE FLAG */
C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 4
148 =2 sbit IT1 = TCON ^ 2; /* EXT. INTERRUPT 1 TYPE */
149 =2 sbit IE0 = TCON ^ 1; /* EXT. INTERRUPT 0 EDGE FLAG */
150 =2 sbit IT0 = TCON ^ 0; /* EXT. INTERRUPT 0 TYPE */
151 =2
152 =2 /* SCON0 0x98 */
153 =2 sbit SM00 = SCON0 ^ 7; /* SERIAL MODE CONTROL BIT 0 */
154 =2 sbit SM10 = SCON0 ^ 6; /* SERIAL MODE CONTROL BIT 1 */
155 =2 sbit SM20 = SCON0 ^ 5; /* MULTIPROCESSOR COMMUNICATION ENABLE */
156 =2 sbit REN0 = SCON0 ^ 4; /* RECEIVE ENABLE */
157 =2 sbit TB80 = SCON0 ^ 3; /* TRANSMIT BIT 8 */
158 =2 sbit RB80 = SCON0 ^ 2; /* RECEIVE BIT 8 */
159 =2 sbit TI0 = SCON0 ^ 1; /* TRANSMIT INTERRUPT FLAG */
160 =2 sbit RI0 = SCON0 ^ 0; /* RECEIVE INTERRUPT FLAG */
161 =2
162 =2 /* IE 0xA8 */
163 =2 sbit EA = IE ^ 7; /* GLOBAL INTERRUPT ENABLE */
164 =2 sbit ET2 = IE ^ 5; /* TIMER 2 INTERRUPT ENABLE */
165 =2 sbit ES0 = IE ^ 4; /* UART0 INTERRUPT ENABLE */
166 =2 sbit ET1 = IE ^ 3; /* TIMER 1 INTERRUPT ENABLE */
167 =2 sbit EX1 = IE ^ 2; /* EXTERNAL INTERRUPT 1 ENABLE */
168 =2 sbit ET0 = IE ^ 1; /* TIMER 0 INTERRUPT ENABLE */
169 =2 sbit EX0 = IE ^ 0; /* EXTERNAL INTERRUPT 0 ENABLE */
170 =2
171 =2 /* IP 0xB8 */
172 =2 sbit PT2 = IP ^ 5; /* TIMER 2 PRIORITY */
173 =2 sbit PS = IP ^ 4; /* SERIAL PORT PRIORITY */
174 =2 sbit PT1 = IP ^ 3; /* TIMER 1 PRIORITY */
175 =2 sbit PX1 = IP ^ 2; /* EXTERNAL INTERRUPT 1 PRIORITY */
176 =2 sbit PT0 = IP ^ 1; /* TIMER 0 PRIORITY */
177 =2 sbit PX0 = IP ^ 0; /* EXTERNAL INTERRUPT 0 PRIORITY */
178 =2
179 =2 /* SMB0CN 0xC0 */
180 =2 sbit BUSY = SMB0CN ^ 7; /* SMBUS 0 BUSY */
181 =2 sbit ENSMB = SMB0CN ^ 6; /* SMBUS 0 ENABLE */
182 =2 sbit STA = SMB0CN ^ 5; /* SMBUS 0 START FLAG */
183 =2 sbit STO = SMB0CN ^ 4; /* SMBUS 0 STOP FLAG */
184 =2 sbit SI = SMB0CN ^ 3; /* SMBUS 0 INTERRUPT PENDING FLAG */
185 =2 sbit AA = SMB0CN ^ 2; /* SMBUS 0 ASSERT/ACKNOWLEDGE FLAG */
186 =2 sbit SMBFTE = SMB0CN ^ 1; /* SMBUS 0 FREE TIMER ENABLE */
187 =2 sbit SMBTOE = SMB0CN ^ 0; /* SMBUS 0 TIMEOUT ENABLE */
188 =2
189 =2 /* T2CON 0xC8 */
190 =2 sbit TF2 = T2CON ^ 7; /* TIMER 2 OVERFLOW FLAG */
191 =2 sbit EXF2 = T2CON ^ 6; /* EXTERNAL FLAG */
192 =2 sbit RCLK0 = T2CON ^ 5; /* UART0 RX CLOCK SOURCE */
193 =2 sbit TCLK0 = T2CON ^ 4; /* UART0 TX CLOCK SOURCE */
194 =2 sbit EXEN2 = T2CON ^ 3; /* TIMER 2 EXTERNAL ENABLE FLAG */
195 =2 sbit TR2 = T2CON ^ 2; /* TIMER 2 ON/OFF CONTROL */
196 =2 sbit CT2 = T2CON ^ 1; /* TIMER OR COUNTER SELECT */
197 =2 sbit CPRL2 = T2CON ^ 0; /* CAPTURE OR RELOAD SELECT */
198 =2
199 =2 /* PSW */
200 =2 sbit CY = PSW ^ 7; /* CARRY FLAG */
201 =2 sbit AC = PSW ^ 6; /* AUXILIARY CARRY FLAG */
202 =2 sbit F0 = PSW ^ 5; /* USER FLAG 0 */
203 =2 sbit RS1 = PSW ^ 4; /* REGISTER BANK SELECT 1 */
204 =2 sbit RS0 = PSW ^ 3; /* REGISTER BANK SELECT 0 */
205 =2 sbit OV = PSW ^ 2; /* OVERFLOW FLAG */
206 =2 sbit F1 = PSW ^ 1; /* USER FLAG 1 */
207 =2 sbit P = PSW ^ 0; /* ACCUMULATOR PARITY FLAG */
208 =2
209 =2 /* PCA0CN D8H */
C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 5
210 =2 sbit CF = PCA0CN ^ 7; /* PCA 0 COUNTER OVERFLOW FLAG */
211 =2 sbit CR = PCA0CN ^ 6; /* PCA 0 COUNTER RUN CONTROL BIT */
212 =2 sbit CCF4 = PCA0CN ^ 4; /* PCA 0 MODULE 4 INTERRUPT FLAG */
213 =2 sbit CCF3 = PCA0CN ^ 3; /* PCA 0 MODULE 3 INTERRUPT FLAG */
214 =2 sbit CCF2 = PCA0CN ^ 2; /* PCA 0 MODULE 2 INTERRUPT FLAG */
215 =2 sbit CCF1 = PCA0CN ^ 1; /* PCA 0 MODULE 1 INTERRUPT FLAG */
216 =2 sbit CCF0 = PCA0CN ^ 0; /* PCA 0 MODULE 0 INTERRUPT FLAG */
217 =2
218 =2 /* ADC0CN E8H */
219 =2 sbit AD0EN = ADC0CN ^ 7; /* ADC 0 ENABLE */
220 =2 sbit AD0TM = ADC0CN ^ 6; /* ADC 0 TRACK MODE */
221 =2 sbit AD0INT = ADC0CN ^ 5; /* ADC 0 CONVERISION COMPLETE INTERRUPT FLAG */
222 =2 sbit AD0BUSY = ADC0CN ^ 4; /* ADC 0 BUSY FLAG */
223 =2 sbit AD0CM1 = ADC0CN ^ 3; /* ADC 0 START OF CONVERSION MODE BIT 1 */
224 =2 sbit AD0CM0 = ADC0CN ^ 2; /* ADC 0 START OF CONVERSION MODE BIT 0 */
225 =2 sbit AD0WINT = ADC0CN ^ 1; /* ADC 0 WINDOW COMPARE INTERRUPT FLAG */
226 =2 sbit AD0LJST = ADC0CN ^ 0; /* ADC 0 RIGHT JUSTIFY DATA BIT */
227 =2
228 =2 /* SPI0CN F8H */
229 =2 sbit SPIF = SPI0CN ^ 7; /* SPI 0 INTERRUPT FLAG */
230 =2 sbit WCOL = SPI0CN ^ 6; /* SPI 0 WRITE COLLISION FLAG */
231 =2 sbit MODF = SPI0CN ^ 5; /* SPI 0 MODE FAULT FLAG */
232 =2 sbit RXOVRN = SPI0CN ^ 4; /* SPI 0 RX OVERRUN FLAG */
233 =2 sbit TXBSY = SPI0CN ^ 3; /* SPI 0 TX BUSY FLAG */
234 =2 sbit SLVSEL = SPI0CN ^ 2; /* SPI 0 SLAVE SELECT */
235 =2 sbit MSTEN = SPI0CN ^ 1; /* SPI 0 MASTER ENABLE */
236 =2 sbit SPIEN = SPI0CN ^ 0; /* SPI 0 SPI ENABLE */
237 =2 #endif //_C8051F020_H_
7 =1 #include "020_IO_PORT.H"
1 =2 #ifndef _020_IO_PORT_H_
2 =2 #define _020_IO_PORT_H_
3 =2
4 =2 sbit p13 = P1^3;
5 =2 sbit p14 = P1^4;
6 =2 sbit p15 = P1^5;
7 =2 sbit p16 = P1^6;
8 =2 sbit p17 = P1^7;
9 =2
10 =2 sbit p20 = P2^0;
11 =2
12 =2 sbit p32 = P3^2;
13 =2 sbit p33 = P3^3;
14 =2
15 =2 sbit p36 = P3^6;
16 =2 sbit p37 = P3^7;
17 =2
18 =2 #endif //_020_IO_PORT_H_
8 =1
9 =1 #include "020_initialize.h"
1 =2 #ifndef _020_INI_H_
2 =2 #define _020_INI_H_
3 =2
4 =2 void Init_Device(void);
5 =2
6 =2 #endif //_020_INI_H_
7 =2 /*
8 =2 //中断次数设定
9 =2 TH0 = ( 65536 - (CRYSTAL_FREQUENCY/12/T0_INT_TIMES_PER_SEC) ) / 256;
10 =2 TL0 = ( 65536 - (CRYSTAL_FREQUENCY/12/T0_INT_TIMES_PER_SEC) ) % 256;
11 =2 TMR3RLL = ( 65536 - (CRYSTAL_FREQUENCY/12/T3_INT_TIMES_PER_SEC) ) % 256;
12 =2 TMR3RLH = ( 65536 - (CRYSTAL_FREQUENCY/12/T3_INT_TIMES_PER_SEC) ) / 256;
13 =2 TMR3L = ( 65536 - (CRYSTAL_FREQUENCY/12/T3_INT_TIMES_PER_SEC) ) % 256;
C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 6
14 =2 TMR3H = ( 65536 - (CRYSTAL_FREQUENCY/12/T3_INT_TIMES_PER_SEC) ) / 256;*/
10 =1 #include "020_interrupt.h"
1 =2 #ifndef _020_INT_H_
2 =2 #define _020_INT_H_
3 =2 //中断向量表
4 =2 //INT0 0
5 =2 //TIMER0 1
6 =2 //INT1 2
7 =2 //TIMER1 3
8 =2 //UART0 4
9 =2 //TIMER2 5
10 =2 //SPI0 6
11 =2 //SMBUS0 7
12 =2 //ADC0越限比较 8
13 =2 //PCA0 9
14 =2 //CP0下降沿 10
15 =2 //CP0上升沿 11
16 =2 //CP1下降沿 12
17 =2 //CP1上升沿 13
18 =2 //TIMER3 14
19 =2 //ADC0转换结束 15
20 =2 //TIMER4 16
21 =2 //ADC1转换结束 17
22 =2 //TIMER6 18
23 =2 //TIMER7 19
24 =2 //UATR1 20
25 =2 //外部晶振准备好 21
26 =2 //
27 =2
28 =2
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