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C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 1
C51 COMPILER V7.50, COMPILATION OF MODULE MAIN
OBJECT MODULE PLACED IN main.OBJ
COMPILER INVOKED BY: C:\Keil\C51\BIN\C51.EXE main.c BROWSE DEBUG OBJECTEXTEND CODE LISTINCLUDE SYMBOLS
line level source
1 #include "include.h"
1 =1 #ifndef _INCLUDE_H_
2 =1 #define _INCLUDE_H_
3 =1
4 =1 #include <intrins.h>
1 =2 /*--------------------------------------------------------------------------
2 =2 INTRINS.H
3 =2
4 =2 Intrinsic functions for C51.
5 =2 Copyright (c) 1988-2004 Keil Elektronik GmbH and Keil Software, Inc.
6 =2 All rights reserved.
7 =2 --------------------------------------------------------------------------*/
8 =2
9 =2 #ifndef __INTRINS_H__
10 =2 #define __INTRINS_H__
11 =2
12 =2 extern void _nop_ (void);
13 =2 extern bit _testbit_ (bit);
14 =2 extern unsigned char _cror_ (unsigned char, unsigned char);
15 =2 extern unsigned int _iror_ (unsigned int, unsigned char);
16 =2 extern unsigned long _lror_ (unsigned long, unsigned char);
17 =2 extern unsigned char _crol_ (unsigned char, unsigned char);
18 =2 extern unsigned int _irol_ (unsigned int, unsigned char);
19 =2 extern unsigned long _lrol_ (unsigned long, unsigned char);
20 =2 extern unsigned char _chkfloat_(float);
21 =2 extern void _push_ (unsigned char _sfr);
22 =2 extern void _pop_ (unsigned char _sfr);
23 =2
24 =2 #endif
25 =2
5 =1
6 =1 #include "C8051F020.H"
1 =2 /*---------------------------------------------------------------------------
2 =2 ; Copyright (C) 2001 CYGNAL INTEGRATED PRODUCTS, INC.
3 =2 ; All rights reserved.
4 =2 ;
5 =2 ;
6 =2 ; FILE NAME : C8051F020.H
7 =2 ; TARGET MCUs : C8051F020, 'F021, 'F022, 'F023
8 =2 ; DESCRIPTION : Register/bit definitions for the C8051F02x product family.
9 =2 ;
10 =2 ; REVISION 1.1
11 =2 ;
12 =2 ;---------------------------------------------------------------------------*/
13 =2 #ifndef _C8051F020_H_
14 =2 #define _C8051F020_H_
15 =2 /* BYTE Registers */
16 =2 sfr P0 = 0x80; /* PORT 0 */
17 =2 sfr SP = 0x81; /* STACK POINTER */
18 =2 sfr DPL = 0x82; /* DATA POINTER - LOW BYTE */
19 =2 sfr DPH = 0x83; /* DATA POINTER - HIGH BYTE */
20 =2 sfr P4 = 0x84; /* PORT 4 */
21 =2 sfr P5 = 0x85; /* PORT 5 */
22 =2 sfr P6 = 0x86; /* PORT 6 */
23 =2 sfr PCON = 0x87; /* POWER CONTROL */
C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 2
24 =2 sfr TCON = 0x88; /* TIMER CONTROL */
25 =2 sfr TMOD = 0x89; /* TIMER MODE */
26 =2 sfr TL0 = 0x8A; /* TIMER 0 - LOW BYTE */
27 =2 sfr TL1 = 0x8B; /* TIMER 1 - LOW BYTE */
28 =2 sfr TH0 = 0x8C; /* TIMER 0 - HIGH BYTE */
29 =2 sfr TH1 = 0x8D; /* TIMER 1 - HIGH BYTE */
30 =2 sfr CKCON = 0x8E; /* CLOCK CONTROL */
31 =2 sfr PSCTL = 0x8F; /* PROGRAM STORE R/W CONTROL */
32 =2 sfr P1 = 0x90; /* PORT 1 */
33 =2 sfr TMR3CN = 0x91; /* TIMER 3 CONTROL */
34 =2 sfr TMR3RLL = 0x92; /* TIMER 3 RELOAD REGISTER - LOW BYTE */
35 =2 sfr TMR3RLH = 0x93; /* TIMER 3 RELOAD REGISTER - HIGH BYTE */
36 =2 sfr TMR3L = 0x94; /* TIMER 3 - LOW BYTE */
37 =2 sfr TMR3H = 0x95; /* TIMER 3 - HIGH BYTE */
38 =2 sfr P7 = 0x96; /* PORT 7 */
39 =2 sfr SCON0 = 0x98; /* SERIAL PORT 0 CONTROL */
40 =2 sfr SBUF0 = 0x99; /* SERIAL PORT 0 BUFFER */
41 =2 sfr SPI0CFG = 0x9A; /* SERIAL PERIPHERAL INTERFACE 0 CONFIGURATION */
42 =2 sfr SPI0DAT = 0x9B; /* SERIAL PERIPHERAL INTERFACE 0 DATA */
43 =2 sfr ADC1 = 0x9C; /* ADC 1 DATA */
44 =2 sfr SPI0CKR = 0x9D; /* SERIAL PERIPHERAL INTERFACE 0 CLOCK RATE CONTROL */
45 =2 sfr CPT0CN = 0x9E; /* COMPARATOR 0 CONTROL */
46 =2 sfr CPT1CN = 0x9F; /* COMPARATOR 1 CONTROL */
47 =2 sfr P2 = 0xA0; /* PORT 2 */
48 =2 sfr EMI0TC = 0xA1; /* EMIF TIMING CONTROL */
49 =2 sfr EMI0CF = 0xA3; /* EXTERNAL MEMORY INTERFACE (EMIF) CONFIGURATION */
50 =2 sfr P0MDOUT = 0xA4; /* PORT 0 OUTPUT MODE CONFIGURATION */
51 =2 sfr P1MDOUT = 0xA5; /* PORT 1 OUTPUT MODE CONFIGURATION */
52 =2 sfr P2MDOUT = 0xA6; /* PORT 2 OUTPUT MODE CONFIGURATION */
53 =2 sfr P3MDOUT = 0xA7; /* PORT 3 OUTPUT MODE CONFIGURATION */
54 =2 sfr IE = 0xA8; /* INTERRUPT ENABLE */
55 =2 sfr SADDR0 = 0xA9; /* SERIAL PORT 0 SLAVE ADDRESS */
56 =2 sfr ADC1CN = 0xAA; /* ADC 1 CONTROL */
57 =2 sfr ADC1CF = 0xAB; /* ADC 1 ANALOG MUX CONFIGURATION */
58 =2 sfr AMX1SL = 0xAC; /* ADC 1 ANALOG MUX CHANNEL SELECT */
59 =2 sfr P3IF = 0xAD; /* PORT 3 EXTERNAL INTERRUPT FLAGS */
60 =2 sfr SADEN1 = 0xAE; /* SERIAL PORT 1 SLAVE ADDRESS MASK */
61 =2 sfr EMI0CN = 0xAF; /* EXTERNAL MEMORY INTERFACE CONTROL */
62 =2 sfr P3 = 0xB0; /* PORT 3 */
63 =2 sfr OSCXCN = 0xB1; /* EXTERNAL OSCILLATOR CONTROL */
64 =2 sfr OSCICN = 0xB2; /* INTERNAL OSCILLATOR CONTROL */
65 =2 sfr P74OUT = 0xB5; /* PORTS 4 - 7 OUTPUT MODE */
66 =2 sfr FLSCL = 0xB6; /* FLASH MEMORY TIMING PRESCALER */
67 =2 sfr FLACL = 0xB7; /* FLASH ACESS LIMIT */
68 =2 sfr IP = 0xB8; /* INTERRUPT PRIORITY */
69 =2 sfr SADEN0 = 0xB9; /* SERIAL PORT 0 SLAVE ADDRESS MASK */
70 =2 sfr AMX0CF = 0xBA; /* ADC 0 MUX CONFIGURATION */
71 =2 sfr AMX0SL = 0xBB; /* ADC 0 MUX CHANNEL SELECTION */
72 =2 sfr ADC0CF = 0xBC; /* ADC 0 CONFIGURATION */
73 =2 sfr P1MDIN = 0xBD; /* PORT 1 INPUT MODE */
74 =2 sfr ADC0L = 0xBE; /* ADC 0 DATA - LOW BYTE */
75 =2 sfr ADC0H = 0xBF; /* ADC 0 DATA - HIGH BYTE */
76 =2 sfr SMB0CN = 0xC0; /* SMBUS 0 CONTROL */
77 =2 sfr SMB0STA = 0xC1; /* SMBUS 0 STATUS */
78 =2 sfr SMB0DAT = 0xC2; /* SMBUS 0 DATA */
79 =2 sfr SMB0ADR = 0xC3; /* SMBUS 0 SLAVE ADDRESS */
80 =2 sfr ADC0GTL = 0xC4; /* ADC 0 GREATER-THAN REGISTER - LOW BYTE */
81 =2 sfr ADC0GTH = 0xC5; /* ADC 0 GREATER-THAN REGISTER - HIGH BYTE */
82 =2 sfr ADC0LTL = 0xC6; /* ADC 0 LESS-THAN REGISTER - LOW BYTE */
83 =2 sfr ADC0LTH = 0xC7; /* ADC 0 LESS-THAN REGISTER - HIGH BYTE */
84 =2 sfr T2CON = 0xC8; /* TIMER 2 CONTROL */
85 =2 sfr T4CON = 0xC9; /* TIMER 4 CONTROL */
C51 COMPILER V7.50 MAIN 05/07/2007 10:34:33 PAGE 3
86 =2 sfr RCAP2L = 0xCA; /* TIMER 2 CAPTURE REGISTER - LOW BYTE */
87 =2 sfr RCAP2H = 0xCB; /* TIMER 2 CAPTURE REGISTER - HIGH BYTE */
88 =2 sfr TL2 = 0xCC; /* TIMER 2 - LOW BYTE */
89 =2 sfr TH2 = 0xCD; /* TIMER 2 - HIGH BYTE */
90 =2 sfr SMB0CR = 0xCF; /* SMBUS 0 CLOCK RATE */
91 =2 sfr PSW = 0xD0; /* PROGRAM STATUS WORD */
92 =2 sfr REF0CN = 0xD1; /* VOLTAGE REFERENCE 0 CONTROL */
93 =2 sfr DAC0L = 0xD2; /* DAC 0 REGISTER - LOW BYTE */
94 =2 sfr DAC0H = 0xD3; /* DAC 0 REGISTER - HIGH BYTE */
95 =2 sfr DAC0CN = 0xD4; /* DAC 0 CONTROL */
96 =2 sfr DAC1L = 0xD5; /* DAC 1 REGISTER - LOW BYTE */
97 =2 sfr DAC1H = 0xD6; /* DAC 1 REGISTER - HIGH BYTE */
98 =2 sfr DAC1CN = 0xD7; /* DAC 1 CONTROL */
99 =2 sfr PCA0CN = 0xD8; /* PCA 0 COUNTER CONTROL */
100 =2 sfr PCA0MD = 0xD9; /* PCA 0 COUNTER MODE */
101 =2 sfr PCA0CPM0 = 0xDA; /* CONTROL REGISTER FOR PCA 0 MODULE 0 */
102 =2 sfr PCA0CPM1 = 0xDB; /* CONTROL REGISTER FOR PCA 0 MODULE 1 */
103 =2 sfr PCA0CPM2 = 0xDC; /* CONTROL REGISTER FOR PCA 0 MODULE 2 */
104 =2 sfr PCA0CPM3 = 0xDD; /* CONTROL REGISTER FOR PCA 0 MODULE 3 */
105 =2 sfr PCA0CPM4 = 0xDE; /* CONTROL REGISTER FOR PCA 0 MODULE 4 */
106 =2 sfr ACC = 0xE0; /* ACCUMULATOR */
107 =2 sfr XBR0 = 0xE1; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 0 */
108 =2 sfr XBR1 = 0xE2; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 1 */
109 =2 sfr XBR2 = 0xE3; /* DIGITAL CROSSBAR CONFIGURATION REGISTER 2 */
110 =2 sfr RCAP4L = 0xE4; /* TIMER 4 CAPTURE REGISTER - LOW BYTE */
111 =2 sfr RCAP4H = 0xE5; /* TIMER 4 CAPTURE REGISTER - HIGH BYTE */
112 =2 sfr EIE1 = 0xE6; /* EXTERNAL INTERRUPT ENABLE 1 */
113 =2 sfr EIE2 = 0xE7; /* EXTERNAL INTERRUPT ENABLE 2 */
114 =2 sfr ADC0CN = 0xE8; /* ADC 0 CONTROL */
115 =2 sfr PCA0L = 0xE9; /* PCA 0 TIMER - LOW BYTE */
116 =2 sfr PCA0CPL0 = 0xEA; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 0 - LOW BYTE */
117 =2 sfr PCA0CPL1 = 0xEB; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 1 - LOW BYTE */
118 =2 sfr PCA0CPL2 = 0xEC; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 2 - LOW BYTE */
119 =2 sfr PCA0CPL3 = 0xED; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 3 - LOW BYTE */
120 =2 sfr PCA0CPL4 = 0xEE; /* CAPTURE/COMPARE REGISTER FOR PCA 0 MODULE 4 - LOW BYTE */
121 =2 sfr RSTSRC = 0xEF; /* RESET SOURCE */
122 =2 sfr B = 0xF0; /* B REGISTER */
123 =2 sfr SCON1 = 0xF1; /* SERIAL PORT 1 CONTROL */
124 =2 sfr SBUF1 = 0xF2; /* SERAIL PORT 1 DATA */
125 =2 sfr SADDR1 = 0xF3; /* SERAIL PORT 1 */
126 =2 sfr TL4 = 0xF4; /* TIMER 4 DATA - LOW BYTE */
127 =2 sfr TH4 = 0xF5; /* TIMER 4 DATA - HIGH BYTE */
128 =2 sfr EIP1 = 0xF6; /* EXTERNAL INTERRUPT PRIORITY REGISTER 1 */
129 =2 sfr EIP2 = 0xF7; /* EXTERNAL INTERRUPT PRIORITY REGISTER 2 */
130 =2 sfr SPI0CN = 0xF8; /* SERIAL PERIPHERAL INTERFACE 0 CONTROL */
131 =2 sfr PCA0H = 0xF9; /* PCA 0 TIMER - HIGH BYTE */
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