sm5.c

基于S3C2410和SM501的彩屏控制器程序

				value += FIELD_GET(regRead32(CRT_FB_WIDTH),
								   CRT_FB_WIDTH,
								   OFFSET)
					  *  (FIELD_GET(regRead32(CRT_VERTICAL_TOTAL),
								   CRT_VERTICAL_TOTAL,
								   DISPLAY_END) + 1);
			}
		}

		// Program panel registers.
		regWrite32(PANEL_FB_ADDRESS,
						  FIELD_SET(0, PANEL_FB_ADDRESS, STATUS, PENDING)	|
						  FIELD_SET(0, PANEL_FB_ADDRESS, EXT, LOCAL)		|
			              FIELD_VALUE(0, PANEL_FB_ADDRESS, ADDRESS, value)	);

		regWrite32(PANEL_FB_WIDTH,
						  FIELD_VALUE(0, PANEL_FB_WIDTH, WIDTH,
									  register_table->fb_width)				|
						  FIELD_VALUE(0, PANEL_FB_WIDTH, OFFSET,
									  register_table->fb_width)				);

		regWrite32(PANEL_WINDOW_WIDTH,
						  FIELD_VALUE(0, PANEL_WINDOW_WIDTH, WIDTH,
									  register_table->width)				|
						  FIELD_VALUE(0, PANEL_WINDOW_WIDTH, X, 0)			);

		regWrite32(PANEL_WINDOW_HEIGHT,
						  FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, HEIGHT, 
									  register_table->height)				|
						  FIELD_VALUE(0, PANEL_WINDOW_HEIGHT, Y, 0)			);

		regWrite32(PANEL_PLANE_TL,
						  FIELD_VALUE(0, PANEL_PLANE_TL, TOP, 0)			|
						  FIELD_VALUE(0, PANEL_PLANE_TL, LEFT, 0)			);

		regWrite32(PANEL_PLANE_BR, 
						  FIELD_VALUE(0, PANEL_PLANE_BR, BOTTOM,
									  register_table->height - 1)			|
						  FIELD_VALUE(0, PANEL_PLANE_BR, RIGHT,
									  register_table->width - 1)			);

		regWrite32(PANEL_HORIZONTAL_TOTAL,
						  register_table->horizontal_total);
		regWrite32(PANEL_HORIZONTAL_SYNC,
						  register_table->horizontal_sync);
		regWrite32(PANEL_VERTICAL_TOTAL,
						  register_table->vertical_total);
		regWrite32(PANEL_VERTICAL_SYNC,
						  register_table->vertical_sync);

		// Program panel display control register.
		value = regRead32(PANEL_DISPLAY_CTRL)
			  & FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE)
			  & FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE)
			  & FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING)
			  & FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE)
			  & FIELD_CLEAR(PANEL_DISPLAY_CTRL, FORMAT);

		regWrite32(PANEL_DISPLAY_CTRL,
						  value | register_table->control);

		// Palette RAM.
		palette_ram = PANEL_PALETTE_RAM;

		// Turn on panel.
		panelPowerSequence(1, 4);
	}

	// Program CRT.
	else
	{
		// Program clock, enable display controller.
		gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE);
		clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SELECT)
			  &  FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_DIVIDER)
			  &  FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SHIFT);
		setPower(gate, clock | register_table->clock);

		// Turn on DAC.
		regWrite32(MISC_CTRL, FIELD_SET(regRead32(MISC_CTRL),
											   MISC_CTRL,
											   DAC_POWER,
											   ENABLE));

		// Calculate frame buffer address.
		value = 0;
		fb_size = register_table->fb_width * register_table->height;
		if (FIELD_GET(regRead32(PANEL_DISPLAY_CTRL),
					  PANEL_DISPLAY_CTRL,
					  PLANE) == PANEL_DISPLAY_CTRL_PLANE_ENABLE)
		{
			value = FIELD_GET(regRead32(PANEL_FB_ADDRESS),
							  PANEL_FB_ADDRESS, 
							  ADDRESS);
			if (fb_size < value)
			{
				value = 0;
			}
			else
			{
				value += FIELD_GET(regRead32(PANEL_FB_WIDTH),
								   PANEL_FB_WIDTH,
								   OFFSET)
					  *  FIELD_GET(regRead32(PANEL_WINDOW_HEIGHT),
								   PANEL_WINDOW_HEIGHT,
								   HEIGHT);
			}
		}

		// Program CRT registers.
		regWrite32(CRT_FB_ADDRESS,
						  FIELD_SET(0, CRT_FB_ADDRESS, STATUS, PENDING)		|
						  FIELD_SET(0, CRT_FB_ADDRESS, EXT, LOCAL)			|
			              FIELD_VALUE(0, CRT_FB_ADDRESS, ADDRESS, value)	);

		regWrite32(CRT_FB_WIDTH,
						  FIELD_VALUE(0, CRT_FB_WIDTH, WIDTH,
									  register_table->fb_width)				|
						  FIELD_VALUE(0, CRT_FB_WIDTH, OFFSET,
									  register_table->fb_width)				);

		regWrite32(CRT_HORIZONTAL_TOTAL,
						  register_table->horizontal_total);
		regWrite32(CRT_HORIZONTAL_SYNC,
						  register_table->horizontal_sync);
		regWrite32(CRT_VERTICAL_TOTAL,
						  register_table->vertical_total);
		regWrite32(CRT_VERTICAL_SYNC,
						  register_table->vertical_sync);

		// Program CRT display control register.
		value = regRead32(CRT_DISPLAY_CTRL)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, SELECT)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, FORMAT);

		regWrite32(CRT_DISPLAY_CTRL,
						  value | register_table->control);

		// Palette RAM.
		palette_ram = CRT_PALETTE_RAM;

		// Turn on CRT.
		setDPMS(DPMS_ON);
	}

	// In case of 8-bpp, fill palette.
	if (FIELD_GET(register_table->control,
				  PANEL_DISPLAY_CTRL,
				  FORMAT) == PANEL_DISPLAY_CTRL_FORMAT_8)
	{
		// Start with RGB = 0,0,0.
		BYTE red = 0, green = 0, blue = 0;
		DWORD gray = 0;
		for (offset = 0; offset < 256 * 4; offset += 4)
		{
			// Store current RGB value.
			regWrite32(palette_ram + offset, gray
								? RGB((gray + 50) / 100,
									  (gray + 50) / 100,
									  (gray + 50) / 100)
								: RGB(red, green, blue));

			if (gray)
			{
				// Walk through grays (40 in total).
				gray += 654;
			}

			else
			{
				// Walk through colors (6 per base color).
				if (blue != 255)
				{
					blue += 51;
				}
				else if (green != 255)
				{
					blue = 0;
					green += 51;
				}
				else if (red != 255)
				{
					green = blue = 0;
					red += 51;
				}
				else
				{
					gray = 1;
				}
			}
		}
	}

	// For 16- and 32-bpp,  fill palette with gamma values.
	else
	{
		// Start with RGB = 0,0,0.
		value = 0x000000;
		for (offset = 0; offset < 256 * 4; offset += 4)
		{
			regWrite32(palette_ram + offset, value);

			// Advance RGB by 1,1,1.
			value += 0x010101;
		}
	}
}
/*
void programMode(reg_table_t *register_table)
{
	unsigned long value, gate, clock;
	unsigned long palette_ram;
	unsigned long fb_size, offset;

	// Get current power configuration.
	gate = regRead32(CURRENT_POWER_GATE);
	clock = regRead32(CURRENT_POWER_CLOCK);
	// Program CRT.
	
	{
		// Program clock, enable display controller.
		gate = FIELD_SET(gate, CURRENT_POWER_GATE, DISPLAY, ENABLE);
		clock &= FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SELECT)
			  &  FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_DIVIDER)
			  &  FIELD_CLEAR(CURRENT_POWER_CLOCK, V2XCLK_SHIFT);
		setPower(gate, clock | register_table->clock);

		// Turn on DAC. modify by kavin very important
		regWrite32(MISC_CTRL, FIELD_SET(0, MISC_CTRL, DAC_POWER, ENABLE) |  FIELD_SET(0, MISC_CTRL, CRYSTAL, 12)
					| FIELD_SET(0, MISC_CTRL, HOST_BUS, XSCALE));
  
		// Calculate frame buffer address.
		value = 0;
		fb_size = register_table->fb_width * register_table->height;
		if (FIELD_GET(regRead32(PANEL_DISPLAY_CTRL),
					  PANEL_DISPLAY_CTRL,
					  PLANE) == PANEL_DISPLAY_CTRL_PLANE_ENABLE)
		{
			value = FIELD_GET(regRead32(PANEL_FB_ADDRESS),
							  PANEL_FB_ADDRESS, 
							  ADDRESS);
							  
			if (fb_size < value)
			{
				value = 0;
			}
			else
			{
				value += FIELD_GET(regRead32(PANEL_FB_WIDTH),
								   PANEL_FB_WIDTH,
								   OFFSET)
					  *  FIELD_GET(regRead32(PANEL_WINDOW_HEIGHT),
								   PANEL_WINDOW_HEIGHT,
								   HEIGHT);
			
			}
		}
		
		// Program CRT registers.
		regWrite32(CRT_FB_ADDRESS,
						  FIELD_SET(0, CRT_FB_ADDRESS, STATUS, CURRENT)		|
						  FIELD_SET(0, CRT_FB_ADDRESS, EXT, LOCAL)			|
						  FIELD_SET(0, CRT_FB_ADDRESS, CS, 1)				|
			              FIELD_VALUE(0, CRT_FB_ADDRESS, ADDRESS, value)	);

		regWrite32(CRT_FB_WIDTH,
						  FIELD_VALUE(0, CRT_FB_WIDTH, WIDTH,
									  register_table->fb_width)				|
						  FIELD_VALUE(0, CRT_FB_WIDTH, OFFSET,
									  register_table->fb_width)				);

		regWrite32(CRT_HORIZONTAL_TOTAL,
						  register_table->horizontal_total);
		regWrite32(CRT_HORIZONTAL_SYNC,
						  register_table->horizontal_sync);
		regWrite32(CRT_VERTICAL_TOTAL,
						  register_table->vertical_total);
		regWrite32(CRT_VERTICAL_SYNC,
						  register_table->vertical_sync);

		// Program CRT display control register.
		value = regRead32(CRT_DISPLAY_CTRL)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, VSYNC_PHASE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, HSYNC_PHASE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, SELECT)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, TIMING)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, PLANE)
			  & FIELD_CLEAR(CRT_DISPLAY_CTRL, FORMAT);

		regWrite32(CRT_DISPLAY_CTRL,
						  value | register_table->control);
		
		// Palette RAM.
		palette_ram = CRT_PALETTE_RAM;
		//palette_ram = PANEL_PALETTE_RAM;

		// Turn on CRT.
		setDPMS(DPMS_ON);
		//FIELD_SET(SYSTEM_CTRL, SYSTEM_CTRL, CRT_TRISTATE, DISABLE);//..
		//FIELD_SET(SYSTEM_CTRL, SYSTEM_CTRL, PANEL_TRISTATE, ENABLE);//..
	}

	// In case of 8-bpp, fill palette.
	if (FIELD_GET(register_table->control,
				  PANEL_DISPLAY_CTRL,
				  FORMAT) == PANEL_DISPLAY_CTRL_FORMAT_8)
	{
		// Start with RGB = 0,0,0.
		unsigned char red = 0, green = 0, blue = 0;
		unsigned long gray = 0;
		for (offset = 0; offset < 256 * 4; offset += 4)
		{
			// Store current RGB value.
			regWrite32(palette_ram + offset, gray
								? RGB((gray + 50) / 100,
									  (gray + 50) / 100,
									  (gray + 50) / 100)
								: RGB(red, green, blue));

			if (gray)
			{
				// Walk through grays (40 in total).
				gray += 654;
			}

			else
			{
				// Walk through colors (6 per base color).
				if (blue != 255)
				{
					blue += 51;
				}
				else if (green != 255)
				{
					blue = 0;
					green += 51;
				}
				else if (red != 255)
				{
					green = blue = 0;
					red += 51;
				}
				else
				{
					gray = 1;
				}
			}
		}
	}

	// For 16- and 32-bpp,  fill palette with gamma values.
	else
	{
		// Start with RGB = 0,0,0.
		value = 0x000000;
		for (offset = 0; offset < 256 * 4; offset += 4)
		{
			regWrite32(palette_ram + offset, value);

			// Advance RGB by 1,1,1.
			value += 0x010101;
		}
	}
}*/

void adjustMode(mode_table_t *vesaMode, mode_table_t *mode, display_t display)
{
	long blank_width, sync_start, sync_width;
	clock_select_t clock;

	// Calculate the VESA line and screen frequencies.
	vesaMode->horizontal_frequency = roundDiv(vesaMode->pixel_clock,
										   vesaMode->horizontal_total);
	vesaMode->vertical_frequency = roundDiv(vesaMode->horizontal_frequency,
										 vesaMode->vertical_total);

	// Calculate the sync percentages of the VESA mode.
	blank_width = vesaMode->horizontal_total
				- vesaMode->horizontal_display_end;
	sync_start = roundDiv((vesaMode->horizontal_sync_start -
					   vesaMode->horizontal_display_end) * 100, blank_width);
	sync_width = roundDiv(vesaMode->horizontal_sync_width * 100, blank_width);

	// Copy VESA mode into Voyager mode.
	*mode = *vesaMode;

	// Find the best pixel clock.
	mode->pixel_clock = findClock(vesaMode->pixel_clock * 2, &clock, display) / 2;

	// Calculate the horizontal total based on the pixel clock and VESA line
	// frequency.
	mode->horizontal_total = roundDiv(mode->pixel_clock,
								   vesaMode->horizontal_frequency);

	// Calculate the sync start and width based on the VESA percentages.
	blank_width = mode->horizontal_total - mode->horizontal_display_end;
	mode->horizontal_sync_start = mode->horizontal_display_end
								+ roundDiv(blank_width * sync_start, 100);
	mode->horizontal_sync_width = roundDiv(blank_width * sync_width, 100);

	// Calculate the line and screen frequencies.
	mode->horizontal_frequency = roundDiv(mode->pixel_clock,
									   mode->horizontal_total);
	mode->vertical_frequency = roundDiv(mode->horizontal_frequency,
									 mode->vertical_total);
}

/*void adjustMode(mode_table_t *vesaMode, mode_table_t *mode, display_t display)
{