📄 nandflash.c
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#define __NANDFLASH
#include "NandFlash.h"
#undef __NANDFLASH
//********************** Global Variable **********************
struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
struct nand_oob_config oob_config = { {0}, 0, 0};
static struct nand_flash_dev nand_flash_ids[] = {
{"Toshiba TC5816BDC", NAND_MFR_TOSHIBA, 0x64, 21, 1, 2, 0x1000},
{"Toshiba TC5832DC", NAND_MFR_TOSHIBA, 0x6b, 22, 0, 2, 0x2000},
{"Toshiba TH58V128DC", NAND_MFR_TOSHIBA, 0x73, 24, 0, 2, 0x4000},
{"Toshiba TC58256FT/DC", NAND_MFR_TOSHIBA, 0x75, 25, 0, 2, 0x4000},
{"Toshiba TH58512FT", NAND_MFR_TOSHIBA, 0x76, 26, 0, 3, 0x4000},
{"Toshiba TC58V32DC", NAND_MFR_TOSHIBA, 0xe5, 22, 0, 2, 0x2000},
{"Toshiba TC58V64AFT/DC", NAND_MFR_TOSHIBA, 0xe6, 23, 0, 2, 0x2000},
{"Toshiba TC58V16BDC", NAND_MFR_TOSHIBA, 0xea, 21, 1, 2, 0x1000},
{"Toshiba TH58100FT", NAND_MFR_TOSHIBA, 0x79, 27, 0, 3, 0x4000},
{"Samsung KM29N16000", NAND_MFR_SAMSUNG, 0x64, 21, 1, 2, 0x1000},
{"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0x6b, 22, 0, 2, 0x2000},
{"Samsung KM29U128T", NAND_MFR_SAMSUNG, 0x73, 24, 0, 2, 0x4000},
{"Samsung KM29U256T", NAND_MFR_SAMSUNG, 0x75, 25, 0, 2, 0x4000},
{"Samsung unknown 64Mb", NAND_MFR_SAMSUNG, 0x76, 26, 0, 3, 0x4000},
{"Samsung KM29W32000", NAND_MFR_SAMSUNG, 0xe3, 22, 0, 2, 0x2000},
{"Samsung unknown 4Mb", NAND_MFR_SAMSUNG, 0xe5, 22, 0, 2, 0x2000},
{"Samsung KM29U64000", NAND_MFR_SAMSUNG, 0xe6, 23, 0, 2, 0x2000},
{"Samsung KM29W16000", NAND_MFR_SAMSUNG, 0xea, 21, 1, 2, 0x1000},
{NULL,}
};
//*************************************************************
//********************** Static Function **********************
/* Current NAND Device */
static int curr_device = -1;
static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip);
static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
static void NanD_ReadBuf(struct nand_chip *nand, u_char *data_buf, int cntr);
static int nand_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf);
static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
size_t * retlen, u_char *buf, u_char *ecc_code);
static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
size_t * retlen, const u_char * buf, u_char * ecc_code);
static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
size_t * retlen, u_char * buf);
static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
size_t * retlen, const u_char * buf);
static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
//*************************************************************
int check_block(struct nand_chip* nand, unsigned long pos)
// returns: 0-block containing pos is OK: valid erase block and not marked bad, or no bad mark position is specified;
// 1-marked bad or otherwise invalid.
{
int retlen;
u8 oob_data;
int page0 = pos & (-nand->erasesize);
int page1 = page0 + nand->oobblock;
int badpos = oob_config.badblock_pos;
if (pos >= nand->totlen)
return 1;
if (badpos < 0)
return 0; /* no way to check, assume OK */
/* Note - bad block marker can be on first or second page */
if (nand_read_oob(nand, page0 + badpos, 1, (size_t *)&retlen, &oob_data) ||
oob_data != 0xff ||
nand_read_oob(nand, page1 + badpos, 1,(size_t *)&retlen, &oob_data) ||
oob_data != 0xff)
return 1;
return 0;
}
/* cmd: 0: NANDRW_WRITE write, fail on bad block
* 1: NANDRW_READ read, fail on bad block
* 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
* 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
*/
static int nand_rw (struct nand_chip* nand, int cmd,
size_t start, size_t len,
size_t * retlen, u_char * buf)
{
int ret = 0, n, total = 0;
char eccbuf[6];
/* eblk (once set) is the start of the erase block containing the
* data being processed.
*/
unsigned long eblk = ~0; /* force mismatch on first pass */
unsigned long erasesize = nand->erasesize;
while (len) {
if ((start & (-erasesize)) != eblk) {
/* have crossed into new erase block, deal with
* it if it is sure marked bad.
*/
eblk = start & (-erasesize); /* start of block */
if (check_block(nand, eblk)) {
if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
while (len > 0 &&
start - eblk < erasesize) {
*(buf++) = 0xff;
++start;
++total;
--len;
}
continue;
}
else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
/* skip bad block */
start += erasesize;
continue;
}
else {
ret = 1;
break;
}
}
}
/* The ECC will not be calculated correctly if
less than 512 is written or read */
/* Is request at least 512 bytes AND it starts on a proper boundry */
if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
if (cmd & NANDRW_READ)
ret = nand_read_ecc(nand, start,
min(len, eblk + erasesize - start),
(size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
else
ret = nand_write_ecc(nand, start,
min(len, eblk + erasesize - start),
(size_t *)&n, (u_char*)buf, (u_char *)eccbuf);
if (ret)
break;
start += n;
buf += n;
total += n;
len -= n;
}
if (retlen)
*retlen = total;
return ret;
}
static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
{
/* This is inline, to optimise the common case, where it's ready instantly */
int ret = 0;
#ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
if(ale_wait)
NAND_WAIT_READY(nand); /* do the worst case 25us wait */
else
udelay(10);
#else /* has functional r/b signal */
NAND_WAIT_READY(nand);
// udelay(25); // 考虑在最坏情形下延时25us
#endif
return ret;
}
/* NanD_Command: Send a flash command to the flash chip */
static __inline int NanD_Command(struct nand_chip *nand, unsigned char command)
{
unsigned long nandptr = nand->IO_ADDR;
/* Assert the CLE (Command Latch Enable) line to the flash chip */
NAND_CTL_SETCLE(nandptr);
/* Send the command */
WRITE_NAND_COMMAND(command, nandptr);
/* Lower the CLE line */
NAND_CTL_CLRCLE(nandptr);
#ifdef NAND_NO_RB
if(command == NAND_CMD_RESET){
u_char ret_val;
NanD_Command(nand, NAND_CMD_STATUS);
do{
ret_val = READ_NAND(nandptr);/* wait till ready */
} while((ret_val & 0x40) != 0x40);
}
#endif
return NanD_WaitReady(nand, 0);
}
/* NanD_Address: Set the current address for the flash chip */
static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
{
unsigned long nandptr;
int i;
nandptr = nand->IO_ADDR;
/* Assert the ALE (Address Latch Enable) line to the flash chip */
NAND_CTL_SETALE(nandptr);
/* Send the address */
/* Devices with 256-byte page are addressed as:
* Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
* there is no device on the market with page256
* and more than 24 bits.
* Devices with 512-byte page are addressed as:
* Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
* 25-31 is sent only if the chip support it.
* bit 8 changes the read command to be sent
* (NAND_CMD_READ0 or NAND_CMD_READ1).
*/
if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
WRITE_NAND_ADDRESS(ofs, nandptr);
ofs = ofs >> nand->page_shift;
if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8)
WRITE_NAND_ADDRESS(ofs, nandptr);
/* Lower the ALE line */
NAND_CTL_CLRALE(nandptr);
/* Wait for the chip to respond */
return NanD_WaitReady(nand, 1);
}
/* NanD_SelectChip: Select a given flash chip within the current floor */
static __inline int NanD_SelectChip(struct nand_chip *nand, int chip)
{
/* Wait for it to be ready */
return NanD_WaitReady(nand, 0);
}
/* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
{
int mfr, id, i;
NAND_ENABLE_CE(nand); /* set pin low */
/* Reset the chip */
if (NanD_Command(nand, NAND_CMD_RESET)) {
NAND_DISABLE_CE(nand); /* set pin high */
return 0;
}
/* Read the NAND chip ID: 1. Send ReadID command */
if (NanD_Command(nand, NAND_CMD_READID)) {
NAND_DISABLE_CE(nand); /* set pin high */
return 0;
}
/* Read the NAND chip ID: 2. Send address byte zero */
NanD_Address(nand, ADDR_COLUMN, 0);
/* Read the manufacturer and device id codes from the device */
mfr = READ_NAND(nand->IO_ADDR);
id = READ_NAND(nand->IO_ADDR);
NAND_DISABLE_CE(nand); /* set pin high */
/* No response - return failure */
if (mfr == 0xff || mfr == 0)
return 0;
/* Check it's the same as the first chip we identified.
* M-Systems say that any given nand_chip device should only
* contain _one_ type of flash part, although that's not a
* hardware restriction. */
if (nand->mfr) {
if (nand->mfr == mfr && nand->id == id)
return 1; /* This is another the same the first */
}
/* Print and store the manufacturer and ID codes. */
for (i = 0; nand_flash_ids[i].name != NULL; i++)
{
if (mfr == nand_flash_ids[i].manufacture_id &&
id == nand_flash_ids[i].model_id)
{
if (!nand->mfr) {
nand->mfr = mfr;
nand->id = id;
nand->chipshift =
nand_flash_ids[i].chipshift;
nand->page256 = nand_flash_ids[i].page256;
nand->eccsize = 256;
if (nand->page256) {
nand->oobblock = 256;
nand->oobsize = 8;
nand->page_shift = 8;
} else {
nand->oobblock = 512;
nand->oobsize = 16;
nand->page_shift = 9;
}
nand->pageadrlen =
nand_flash_ids[i].pageadrlen;
nand->erasesize =
nand_flash_ids[i].erasesize;
memcpy(nand->chips_name,nand_flash_ids[i].name,64);
/*nand->chips_name =
nand_flash_ids[i].name;*/
return 1;
}
return 0;
}
}
return 0;
}
/* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
static void NanD_ScanChips(struct nand_chip *nand)
{
int floor, chip;
int numchips[NAND_MAX_FLOORS];
int maxchips = NAND_MAX_CHIPS;
int ret = 1;
nand->numchips = 0;
nand->mfr = 0;
nand->id = 0;
/* For each floor, find the number of valid chips it contains */
for (floor = 0; floor < NAND_MAX_FLOORS; floor++)
{
ret = 1;
numchips[floor] = 0;
for (chip = 0; chip < maxchips && ret != 0; chip++)
{
ret = NanD_IdentChip(nand, floor, chip);
if (ret)
{
numchips[floor]++;
nand->numchips++;
}
}
}
/* If there are none at all that we recognise, bail */
if (!nand->numchips)
return;
/* Allocate an array to hold the information for each chip */
//nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
if (!nand->chips)
return;
ret = 0;
/* Fill out the chip array with {floor, chipno} for each
* detected chip in the device. */
for (floor = 0; floor < NAND_MAX_FLOORS; floor++)
{
for (chip = 0; chip < numchips[floor]; chip++)
{
nand->chips[ret].floor = floor;
nand->chips[ret].chip = chip;
nand->chips[ret].curadr = 0;
nand->chips[ret].curmode = 0x50;
ret++;
}
}
/* Calculate and print the total size of the device */
nand->totlen = nand->numchips * (1 << nand->chipshift);
}//NanD_ScanChips()
/* we need to be fast here, 1 us per read translates to 1 second per meg */
static void NanD_ReadBuf(struct nand_chip *nand, u_char *data_buf, int cntr)
{
unsigned long nandptr = nand->IO_ADDR;
while (cntr >= 16) {
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
*data_buf++ = READ_NAND(nandptr);
cntr -= 16;
}
while (cntr > 0) {
*data_buf++ = READ_NAND(nandptr);
cntr--;
}
}
/*
* NAND read with ECC
*/
static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
size_t * retlen, u_char *buf, u_char *ecc_code)
{
int col, page;
int ecc_status = 0;
#ifdef CONFIG_MTD_NAND_ECC
int j;
int ecc_failed = 0;
u_char *data_poi;
u_char ecc_calc[6];
#endif
/* Do not allow reads past end of device */
if ((start + len) > nand->totlen) {
//printf ("%s: Attempt read beyond end of device %x %x %x\n", __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
*retlen = 0;
return -1;
}
/* First we calculate the starting page */
/*page = shr(start, nand->page_shift);*/
page = start >> nand->page_shift;
/* Get raw starting column */
col = start & (nand->oobblock - 1);
/* Initialize return value */
*retlen = 0;
/* Select the NAND device */
NAND_ENABLE_CE(nand); /* set pin low */
/* Loop until all data read */
while (*retlen < len) {
#ifdef CONFIG_MTD_NAND_ECC
/* Do we have this page in cache ? */
if (nand->cache_page == page)
goto readdata;
/* Send the read command */
NanD_Command(nand, NAND_CMD_READ0);
NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
/* Read in a page + oob data */
NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
/* copy data into cache, for read out of cache and if ecc fails */
if (nand->data_cache)
memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize);
/* Pick the ECC bytes out of the oob data */
for (j = 0; j < 6; j++)
ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
/* Calculate the ECC and verify it */
/* If block was not written with ECC, skip ECC */
if (oob_config.eccvalid_pos != -1 &&
(nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
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