📄 sm5.h
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#define GPIO_MUX_LOW_14_GPIO 0#define GPIO_MUX_LOW_14_8051 1#define GPIO_MUX_LOW_13 13:13#define GPIO_MUX_LOW_13_GPIO 0#define GPIO_MUX_LOW_13_8051 1#define GPIO_MUX_LOW_12 12:12#define GPIO_MUX_LOW_12_GPIO 0#define GPIO_MUX_LOW_12_8051 1#define GPIO_MUX_LOW_11 11:11#define GPIO_MUX_LOW_11_GPIO 0#define GPIO_MUX_LOW_11_8051 1#define GPIO_MUX_LOW_10 10:10#define GPIO_MUX_LOW_10_GPIO 0#define GPIO_MUX_LOW_10_8051 1#define GPIO_MUX_LOW_9 9:9#define GPIO_MUX_LOW_9_GPIO 0#define GPIO_MUX_LOW_9_8051 1#define GPIO_MUX_LOW_8 8:8#define GPIO_MUX_LOW_8_GPIO 0#define GPIO_MUX_LOW_8_8051 1#define GPIO_MUX_LOW_7 7:7#define GPIO_MUX_LOW_7_GPIO 0#define GPIO_MUX_LOW_7_8051 1#define GPIO_MUX_LOW_6 6:6#define GPIO_MUX_LOW_6_GPIO 0#define GPIO_MUX_LOW_6_8051 1#define GPIO_MUX_LOW_5 5:5#define GPIO_MUX_LOW_5_GPIO 0#define GPIO_MUX_LOW_5_8051 1#define GPIO_MUX_LOW_4 4:4#define GPIO_MUX_LOW_4_GPIO 0#define GPIO_MUX_LOW_4_8051 1#define GPIO_MUX_LOW_3 3:3#define GPIO_MUX_LOW_3_GPIO 0#define GPIO_MUX_LOW_3_8051 1#define GPIO_MUX_LOW_2 2:2#define GPIO_MUX_LOW_2_GPIO 0#define GPIO_MUX_LOW_2_8051 1#define GPIO_MUX_LOW_1 1:1#define GPIO_MUX_LOW_1_GPIO 0#define GPIO_MUX_LOW_1_8051 1#define GPIO_MUX_LOW_0 0:0#define GPIO_MUX_LOW_0_GPIO 0#define GPIO_MUX_LOW_0_8051 1#define GPIO_MUX_HIGH 0x00000C#define GPIO_MUX_HIGH_63 31:31#define GPIO_MUX_HIGH_63_GPIO 0#define GPIO_MUX_HIGH_63_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_62 30:30#define GPIO_MUX_HIGH_62_GPIO 0#define GPIO_MUX_HIGH_62_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_61 29:29#define GPIO_MUX_HIGH_61_GPIO 0#define GPIO_MUX_HIGH_61_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_60 28:28#define GPIO_MUX_HIGH_60_GPIO 0#define GPIO_MUX_HIGH_60_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_59 27:27#define GPIO_MUX_HIGH_59_GPIO 0#define GPIO_MUX_HIGH_59_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_58 26:26#define GPIO_MUX_HIGH_58_GPIO 0#define GPIO_MUX_HIGH_58_CRT_ZVPORT_FPDATA 1#define GPIO_MUX_HIGH_57 25:25#define GPIO_MUX_HIGH_57_GPIO 0#define GPIO_MUX_HIGH_57_CRT_ZVPORT 1#define GPIO_MUX_HIGH_56 24:24#define GPIO_MUX_HIGH_56_GPIO 0#define GPIO_MUX_HIGH_56_CRT_ZVPORT 1#define GPIO_MUX_HIGH_55 23:23#define GPIO_MUX_HIGH_55_GPIO 0#define GPIO_MUX_HIGH_55_CRT 1#define GPIO_MUX_HIGH_47 15:15#define GPIO_MUX_HIGH_47_GPIO 0#define GPIO_MUX_HIGH_47_I2C 1#define GPIO_MUX_HIGH_46 14:14#define GPIO_MUX_HIGH_46_GPIO 0#define GPIO_MUX_HIGH_46_I2C 1#define GPIO_MUX_HIGH_45 13:13#define GPIO_MUX_HIGH_45_GPIO 0#define GPIO_MUX_HIGH_45_SSP1 1#define GPIO_MUX_HIGH_44 12:12#define GPIO_MUX_HIGH_44_GPIO 0#define GPIO_MUX_HIGH_44_UART1_SSP1 1#define GPIO_MUX_HIGH_43 11:11#define GPIO_MUX_HIGH_43_GPIO 0#define GPIO_MUX_HIGH_43_UART1_SSP1 1#define GPIO_MUX_HIGH_42 10:10#define GPIO_MUX_HIGH_42_GPIO 0#define GPIO_MUX_HIGH_42_UART1_SSP1 1#define GPIO_MUX_HIGH_41 9:9#define GPIO_MUX_HIGH_41_GPIO 0#define GPIO_MUX_HIGH_41_UART1_SSP1 1#define GPIO_MUX_HIGH_40 8:8#define GPIO_MUX_HIGH_40_GPIO 0#define GPIO_MUX_HIGH_40_UART0 1#define GPIO_MUX_HIGH_39 7:7#define GPIO_MUX_HIGH_39_GPIO 0#define GPIO_MUX_HIGH_39_UART0 1#define GPIO_MUX_HIGH_38 6:6#define GPIO_MUX_HIGH_38_GPIO 0#define GPIO_MUX_HIGH_38_UART0 1#define GPIO_MUX_HIGH_37 5:5#define GPIO_MUX_HIGH_37_GPIO 0#define GPIO_MUX_HIGH_37_UART0 1#define GPIO_MUX_HIGH_36 4:4#define GPIO_MUX_HIGH_36_GPIO 0#define GPIO_MUX_HIGH_36_SSP0 1#define GPIO_MUX_HIGH_35 3:3#define GPIO_MUX_HIGH_35_GPIO 0#define GPIO_MUX_HIGH_35_SSP0 1#define GPIO_MUX_HIGH_34 2:2#define GPIO_MUX_HIGH_34_GPIO 0#define GPIO_MUX_HIGH_34_SSP0 1#define GPIO_MUX_HIGH_33 1:1#define GPIO_MUX_HIGH_33_GPIO 0#define GPIO_MUX_HIGH_33_SSP0 1#define GPIO_MUX_HIGH_32 0:0#define GPIO_MUX_HIGH_32_GPIO 0#define GPIO_MUX_HIGH_32_SSP0 1#define DRAM_CTRL 0x000010#define DRAM_CTRL_EMBEDDED 31:31#define DRAM_CTRL_EMBEDDED_ENABLE 0#define DRAM_CTRL_EMBEDDED_DISABLE 1#define DRAM_CTRL_CPU_BURST 30:28#define DRAM_CTRL_CPU_BURST_1 0#define DRAM_CTRL_CPU_BURST_2 1#define DRAM_CTRL_CPU_BURST_4 2#define DRAM_CTRL_CPU_BURST_8 3#define DRAM_CTRL_CPU_CAS_LATENCY 27:27#define DRAM_CTRL_CPU_CAS_LATENCY_2 0#define DRAM_CTRL_CPU_CAS_LATENCY_3 1#define DRAM_CTRL_CPU_SIZE 26:24#define DRAM_CTRL_CPU_SIZE_2 0#define DRAM_CTRL_CPU_SIZE_4 1#define DRAM_CTRL_CPU_SIZE_64 4#define DRAM_CTRL_CPU_SIZE_32 5#define DRAM_CTRL_CPU_SIZE_16 6#define DRAM_CTRL_CPU_SIZE_8 7#define DRAM_CTRL_CPU_COLUMN_SIZE 23:22#define DRAM_CTRL_CPU_COLUMN_SIZE_1024 0#define DRAM_CTRL_CPU_COLUMN_SIZE_512 2#define DRAM_CTRL_CPU_COLUMN_SIZE_256 3#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE 21:21#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_6 0#define DRAM_CTRL_CPU_ACTIVE_PRECHARGE_7 1#define DRAM_CTRL_CPU_RESET 20:20#define DRAM_CTRL_CPU_RESET_ENABLE 0#define DRAM_CTRL_CPU_RESET_DISABLE 1#define DRAM_CTRL_CPU_BANKS 19:19#define DRAM_CTRL_CPU_BANKS_2 0#define DRAM_CTRL_CPU_BANKS_4 1#define DRAM_CTRL_CPU_WRITE_PRECHARGE 18:18#define DRAM_CTRL_CPU_WRITE_PRECHARGE_2 0#define DRAM_CTRL_CPU_WRITE_PRECHARGE_1 1#define DRAM_CTRL_BLOCK_WRITE 17:17#define DRAM_CTRL_BLOCK_WRITE_DISABLE 0#define DRAM_CTRL_BLOCK_WRITE_ENABLE 1#define DRAM_CTRL_REFRESH_COMMAND 16:16#define DRAM_CTRL_REFRESH_COMMAND_10 0#define DRAM_CTRL_REFRESH_COMMAND_12 1#define DRAM_CTRL_SIZE 15:13#define DRAM_CTRL_SIZE_4 0#define DRAM_CTRL_SIZE_8 1#define DRAM_CTRL_SIZE_16 2#define DRAM_CTRL_SIZE_32 3#define DRAM_CTRL_SIZE_64 4#define DRAM_CTRL_SIZE_2 5#define DRAM_CTRL_COLUMN_SIZE 12:11#define DRAM_CTRL_COLUMN_SIZE_256 0#define DRAM_CTRL_COLUMN_SIZE_512 2#define DRAM_CTRL_COLUMN_SIZE_1024 3#define DRAM_CTRL_BLOCK_WRITE_TIME 10:10#define DRAM_CTRL_BLOCK_WRITE_TIME_1 0#define DRAM_CTRL_BLOCK_WRITE_TIME_2 1#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE 9:9#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_4 0#define DRAM_CTRL_BLOCK_WRITE_PRECHARGE_1 1#define DRAM_CTRL_ACTIVE_PRECHARGE 8:8#define DRAM_CTRL_ACTIVE_PRECHARGE_6 0#define DRAM_CTRL_ACTIVE_PRECHARGE_7 1#define DRAM_CTRL_RESET 7:7#define DRAM_CTRL_RESET_ENABLE 0#define DRAM_CTRL_RESET_DISABLE 1#define DRAM_CTRL_REMAIN_ACTIVE 6:6#define DRAM_CTRL_REMAIN_ACTIVE_ENABLE 0#define DRAM_CTRL_REMAIN_ACTIVE_DISABLE 1#define DRAM_CTRL_BANKS 1:1#define DRAM_CTRL_BANKS_2 0#define DRAM_CTRL_BANKS_4 1#define DRAM_CTRL_WRITE_PRECHARGE 0:0#define DRAM_CTRL_WRITE_PRECHARGE_2 0#define DRAM_CTRL_WRITE_PRECHARGE_1 1#define ARBITRATION_CTRL 0x000014#define ARBITRATION_CTRL_CPUMEM 29:29#define ARBITRATION_CTRL_CPUMEM_FIXED 0#define ARBITRATION_CTRL_CPUMEM_ROTATE 1#define ARBITRATION_CTRL_INTMEM 28:28#define ARBITRATION_CTRL_INTMEM_FIXED 0#define ARBITRATION_CTRL_INTMEM_ROTATE 1#define ARBITRATION_CTRL_USB 27:24#define ARBITRATION_CTRL_USB_OFF 0#define ARBITRATION_CTRL_USB_PRIORITY_1 1#define ARBITRATION_CTRL_USB_PRIORITY_2 2#define ARBITRATION_CTRL_USB_PRIORITY_3 3#define ARBITRATION_CTRL_USB_PRIORITY_4 4#define ARBITRATION_CTRL_USB_PRIORITY_5 5#define ARBITRATION_CTRL_USB_PRIORITY_6 6#define ARBITRATION_CTRL_USB_PRIORITY_7 7#define ARBITRATION_CTRL_PANEL 23:20#define ARBITRATION_CTRL_PANEL_OFF 0#define ARBITRATION_CTRL_PANEL_PRIORITY_1 1#define ARBITRATION_CTRL_PANEL_PRIORITY_2 2#define ARBITRATION_CTRL_PANEL_PRIORITY_3 3#define ARBITRATION_CTRL_PANEL_PRIORITY_4 4#define ARBITRATION_CTRL_PANEL_PRIORITY_5 5#define ARBITRATION_CTRL_PANEL_PRIORITY_6 6#define ARBITRATION_CTRL_PANEL_PRIORITY_7 7#define ARBITRATION_CTRL_ZVPORT 19:16#define ARBITRATION_CTRL_ZVPORT_OFF 0#define ARBITRATION_CTRL_ZVPORT_PRIORITY_1 1#define ARBITRATION_CTRL_ZVPORT_PRIORITY_2 2#define ARBITRATION_CTRL_ZVPORT_PRIORITY_3 3#define ARBITRATION_CTRL_ZVPORT_PRIORITY_4 4#define ARBITRATION_CTRL_ZVPORT_PRIORITY_5 5#define ARBITRATION_CTRL_ZVPORT_PRIORITY_6 6#define ARBITRATION_CTRL_ZVPORT_PRIORITY_7 7#define ARBITRATION_CTRL_CMD_INTPR 15:12#define ARBITRATION_CTRL_CMD_INTPR_OFF 0#define ARBITRATION_CTRL_CMD_INTPR_PRIORITY_1 1⌨️ 快捷键说明
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