at24c02.v

at24c0x读写控制模块 支持单字节读写和页读写

      S_send_rcvb = receive;
      //Get_MSB_Byte_and_ACK;
      Get_LSB_Byte_and_ACK;
   end
endtask 

task Begin_a_Read_Sequence;
 begin 
   @ (negedge scl)
   shift_in = 0;
   NO_ACK_flag = 0;
   Check_for_Valid_Device_Address;
    if (Valid_Device_Address)
        begin: Device_Address_Match 
           $display ("Device Address Match");
           case (S_Byte_Shft_Reg[0]) 
           0: Write_or_Dummy_Write_with_Random_Read;  // Should not occur
           1: Read_After_Dummy_Write;	   // For READ after a dummy write
           default: $display("Invalid Read protocol sequence received");
           endcase
        end  // Device_Address_Match
 end
endtask

task Execute_page_Write;
  begin
   while (S_STOP != 1)
       begin: Page_Write
        $display("********************************Page write");
         shift_in = 1;
         @ (posedge scl);
         @ (negedge scl)
           if (S_STOP ==1)
             begin
              TOFG = 1;
              shift_in = 0;
              $display("STOP detected - and begin time out for writing"); 
             end
           else
             begin
               repeat (7) @ (posedge scl);
               ACK_and_write_a_Byte;
               addr_reg[7:0] <= addr_reg[7:0] +1;     
               $display("Increment the address register LSB byte");
             end
       end // Page_Write
   end
endtask

task Current_Address_and_Sequential_Read;
   begin
      $display("Beginning Current_Address_and_Sequential_Read");
      Load_Slave_Shift_Register_and_Send_ACK;
      shift_out = 1; 
      @(negedge scl); 
      forever begin :Current_or_Sequential_Read
          repeat (7) @ (negedge scl); // Have sent ACK and 8 bits to master
          shift_out = 0;
          ld_S_Byte_Shft_Reg = 1; 
           S_send_rcvb = receive;
          ->incr_addr_reg;
          @ (posedge scl)
          if (sda_in > 0) 
             begin :Got_NO_ACK_from_Master
               NO_ACK_so_wait_for_STOP_condition;
               disable MACHINE_LOOP.Main_Loop; 
               end //Got_No_ACK_from_Master
          else 
              begin: Got_ACK_from_Master  //  bit was 0
                 Got_ACK_so_prepare_to_send;
              end // Got_ACK_from_Master
      end // Current _or_Sequential_Read 
  end
endtask

task Read_After_Dummy_Write;
   begin
     $display("Reading After Dummy Write");
     Load_Slave_Shift_Register_and_Send_ACK;
         forever 
          begin :Current_or_Sequential_Read
             shift_out = 1; S_send_rcvb = send;
             repeat (8) @ (posedge scl);   // have sent ACK and 8 bits to master
             @ (negedge scl)shift_out = 0;
             ld_S_Byte_Shft_Reg = 1; 
             S_send_rcvb = receive;
             ->incr_addr_reg;
             @ (posedge scl)
             if (sda_in > 0)
                 begin :Got_NO_ACK_from_Master
                    NO_ACK_so_wait_for_STOP_condition;
                    disable MACHINE_LOOP.Main_Loop; 
                 end //Got_No_ACK_from_Master

        else
           begin: Got_ACK_from_Master  //  bit was 0
             $display ("got ACK from master");
              @ (negedge scl);
              ld_S_Byte_Shft_Reg = 0;
              S_send_rcvb = send;
              shift_out = 1;
            end // Got_ACK_from_Master
        end // Current _or_Sequential_Read 
    end
endtask

task Load_Slave_Shift_Register_and_Send_ACK;
    begin
      ld_S_Byte_Shft_Reg = 1;
      S_send_rcvb = send;
      S_ACK = 1;                             // Send ACK to master
      @(negedge scl) 
      ld_S_Byte_Shft_Reg = 0;
       S_ACK = 0;
    end
endtask

task Got_ACK_so_prepare_to_send;
   begin
     $display ("got ACK from master");
     @ (negedge scl);
     ld_S_Byte_Shft_Reg = 0;
     S_send_rcvb = send;
     shift_out = 1;
     @ (negedge scl) ;
   end
endtask

task NO_ACK_so_wait_for_STOP_condition;
   begin
     NO_ACK_flag = 1; $display ("Got_NO_ACK_from_Master ");
     ld_S_Byte_Shft_Reg = 0;
     @ (S_STOP_condition)
       begin // 
         $display ("disable Main_Loop"); 
         NO_ACK_flag = 0; 
       end
   end
endtask                   

//task Get_MSB_Byte_and_ACK;
//  begin
//    Get_a_Byte;
//    @ (negedge scl) ;
//    shift_in = 0;
//    ld_addr_reg_byte = 1;
//    S_send_rcvb = send;
//    S_ACK = 1; 				// Send ACK to master
//    @ (negedge scl) 
//    $display                      ("Loading MSB address byte");
//    ld_addr_reg_byte = 0; 
//    S_send_rcvb = receive;
//    S_ACK = 0;
//  end
//endtask


task Get_LSB_Byte_and_ACK;
   begin
      shift_in = 1;
      Get_a_Byte;
      @ (negedge scl) ;
      shift_in = 0;
      ld_addr_reg_LSB_byte = 1;
      S_send_rcvb = send;
      S_ACK = 1;                      // Send ACK to master
      @ (negedge scl) 
      $display                       ("Loading LSB address byte");
      ld_addr_reg_LSB_byte = 0; 
      S_send_rcvb = receive;
      S_ACK = 0; 
   end
endtask

task Power_up_initialization;		
  begin
    #1 $display ("Power_up_Initialization");
    addr_reg = 0;
    S_send_rcvb = receive;
    ld_S_Byte_Shft_Reg = 0;    
    ld_addr_reg_LSB_byte = 0;
    shift_in = 0;
    shift_out = 0;
    S_ACK = 0;
    NO_ACK_flag = 0;
    TOFG = 0;
    S_START = 0;
    S_STOP = 0;
  end
endtask


//***************************************************************************
//***************************************************************************
//                           Timing Parameters and Checks                             
//***************************************************************************
//***************************************************************************   
/*     __________________________________________________                   *  
*     | Symbol  |  Voltage   |  Min   |  Max  |  Units |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  fscl   |  4.5 - 5.5 |   0    |  400  |   kHz  |                    *
*     |         |  2.7 - 5.5 |   0    |  100  |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  tLOW   |  4.5 - 5.5 |   0.6  |   0   |   us   |                    *
*     |         |  2.7 - 5.5 |   1.3  |   0   |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  tHIGH  |  4.5 - 5.5 |   0.4  |   0   |   us   |                    *
*     |         |  2.7 - 5.5 |   1.0  |   0   |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  tAA    |  4.5 - 5.5 |   0.05 |  0.05 |   us   |                    *
*     |         |  2.7 - 5.5 |   0.05 |  0.9  |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     | tHDSTA  |  4.5 - 5.5 |   0.25 |       |   us   |                    *
*     |         |  2.7 - 5.5 |   0.6  |       |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     | tSUSTA  |  4.5 - 5.5 |   0.25 |       |   us   |                    *
*     |         |  2.7 - 5.5 |   0.6  |       |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     | tHDDAT  |            |        |   0   |   ns   |                    *
*     |---------|------------|--------|-------|--------|                    *
*     | tSUDAT  |            |        |   100 |   ns   |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  tSUSTO |  4.5 - 5.5 |   0.25 |       |   us   |                    *
*     |         |  2.7 - 5.5 |   0.6  |       |        |                    *
*     |---------|------------|--------|-------|--------|                    *
*     |  tDH    |            |   50   |       |   ns   |                    *
*      ------------------------------------------------                     *
*                                                                           *
****************************************************************************/


specify             
  specparam tLOW    = 600;     
  specparam tHIGH   = 400;
  //specparam tAA     = 50;
  specparam tHDSTA  = 250;  
  specparam tSUSTA  = 250;
  specparam tHDDAT  = 0;
  specparam tSUDAT  = 100;   
  specparam tSYSTO  = 300;
  specparam tSU     = 250;
  specparam tDH     = 50;   
endspecify

endmodule