i2c_tb.v

at24c0x读写控制模块 支持单字节读写和页读写

`timescale 1ns / 10 ps
module i2c_tb  ; 


  wire  [7:0]  i2c_rbuf   ; 
  reg    read   ; 
  wire   next_wrdata   ; 
  wire   read_done;
  reg    rst   ; 
  reg  [7:0]  byte_addr   ; 
  reg  [7:0]  i2c_tbuf   ; 
  wire    scl   ; 
  tri   sda_in   ; 
  reg    clk   ;    
  reg    write   ; 
  wire    sda_out,  en ; 
  i2c    //#( w_data , r_ack , slave_waddr , tp , x_stop , w_ack , x_start , x_idle , r_data , slave_raddr  )
   DUT  ( 
      .i2c_rbuf (i2c_rbuf ) ,
      .read (read ) , 
      .en(en), 
      .rst (rst ) ,
      .byte_addr (byte_addr ) ,
      .i2c_tbuf (i2c_tbuf ) ,
      .scl (scl ) ,
      .sda_in (sda_in ) ,
      .clk (clk ) ,
      .write (write ) ,
      .read_done(read_done),
      .next_wrdata(next_wrdata),
      .sda_out (sda_out ) ); 
      
//***************************************************
  tri sda;						// Serial data
  //input scl;						// Serial clock
  wire wp;						     // Write protection   
  
AT24C02 dut1(
  sda,
  scl,
  wp);
  assign sda=(en)? sda_out:1'bz;  
  assign sda_in=sda;
  assign wp=0;
//************************************************   
//////////////////////////////////////////////////////////////
//????
parameter w_data  = 4 ;
parameter r_ack  = 5 ;
parameter slave_waddr  = 160 ;
parameter tp  = 1 ;
parameter x_stop  = 8 ;
parameter w_ack  = 7 ;  
parameter x_start  = 2 ;
parameter repeat_s= 3;
parameter x_idle  = 1 ;
parameter r_data  = 6 ;
parameter slave_raddr  = 161 ; 
/////////////////////////////////////////////////////////////
//????
parameter clk_period=6450;
parameter n=2;
parameter rst_time=n*clk_period;
   
initial
begin
   clk=0;
   forever
     
     #((clk_period)/2) clk=~clk;
end
initial
begin
    rst=0;  
    #rst_time rst=1; 
 end 
 //////////////////////////////////////////////////////////////////
 //???????
 parameter xx_idle=3'b001;
 parameter write_data=3'b010;
 parameter read_data=3'b011;
 parameter xx_stop=3'b100;
 reg [3:0] state;
 
 wire wr_over,read_over;
 assign wr_over=(state==write_data && ~write);
 assign read_over=(state==read_data && ~read);
 always @(posedge clk or negedge rst)
   begin
    if(~rst)   state<=#tp xx_idle;  
    else
    begin
      case(state)
        xx_idle: state<=#tp write_data;  
        write_data:if(wr_over) state<=#tp read_data;
        read_data:if(read_over) state<=#tp xx_stop;
        xx_stop:;
        default:state<=#tp xx_idle;
      endcase
    end
  end
  //***************************************
  reg [4:0] data_cnt;
  reg [7:0] rr_data;
  always @(posedge clk or negedge rst)
   begin
    if(~rst)   
      begin
        write<=#tp 0;
        read<=#tp 0;
        data_cnt<=#tp 0;
        i2c_tbuf<=#tp 8'h00;
      end
    else
    begin   
      case(state)
        xx_idle:
          begin
            write<=#tp 1;
            read<=#tp 0;  
            
          end  
        write_data:
          begin
            if(~wr_over)
            begin
            write<=#tp 1;
            read<=#tp 0;
            byte_addr<=#tp 8'h01;  
            if(next_wrdata) //i2c_tbuf<=#tp 8'h50;
              begin
                data_cnt<=#tp data_cnt+1;
                case(data_cnt)
                  0:i2c_tbuf<=#tp 8'h51;
                  1:i2c_tbuf<=#tp 8'h52;
                  2:i2c_tbuf<=#tp 8'h53;
                  3:i2c_tbuf<=#tp 8'h54;
                  4:i2c_tbuf<=#tp 8'h55;
                  5:begin
                      i2c_tbuf<=#tp 8'h56;
                      write<=#tp 0;
                      read<=#tp 1;
                      data_cnt<=#tp 0; 
                    end
          
                  default: write<=#tp 0;
                endcase
              end
            end
          end
        read_data:
           begin
            write<=#tp 0;
            //read<=#tp 1;
            byte_addr<=#tp 8'h01;  
           //i2c_tbuf<=#tp 8'h50;
            if(read_done) 
              begin
                rr_data<=#tp i2c_rbuf; 
                data_cnt<=#tp data_cnt+1;
                if(data_cnt>=5) read<=#tp 0;
              end
          end
        xx_stop:read<=#tp 0;
        default:;
      endcase
    end
  end
endmodule