u-boot-1.1.4-imx21-jk1.patch

针对freescale imx21的linux2.6的补丁。因为官方只提供2.4内核

+
+#include <config.h>
+#include <version.h>
+#include <asm/arch/imx21-regs.h>
+
+_TEXT_BASE:
+	.word   TEXT_BASE
+
+.globl lowlevel_init
+lowlevel_init:
+	mov	r5, lr
+
+/* For LED */
+        ldr     r1,=CS1U
+        ldr     r0,=0x00002000
+        str     r0,[r1]
+        ldr     r1,=CS1L
+        ldr     r0,=0x11118501
+        str     r0,[r1]
+
+        ldr     r1,=AIPI0_PSR0
+        ldr     r0,=0x00040304
+        str     r0,[r1]
+
+        ldr     r1,=AIPI1_PSR0
+        ldr     r0,=0x00000000
+        str     r0,[r1]
+
+        ldr     r1,=AIPI0_PSR1
+        ldr     r0,=0xFFFBFCFB
+        str     r0,[r1]
+
+        ldr     r1,=AIPI1_PSR1
+        ldr     r0,=0xFFFFFFFF
+        str     r0,[r1]
+	
+        /* write to the FMCR [31:24] (CLKMODE[1:0])
+         * in order to get the write enable signal active
+         */
+
+        ldr     r1,=SYSCTL_FMCR
+        ldr     r0, [r1]
+        orr     r0, r0, #0xAA000000
+        str     r0, [r1]
+
+   	/*
+         * disable interrupts
+         */
+        ldr     r1, =AITC_INTENABLEH    @ disable high interrupts
+        mov     r0, #0
+        str     r0, [r1]
+
+        ldr     r1, =AITC_INTENABLEL    @ disable low interrupts
+        str     r0, [r1]
+
+	/* MPLL */
+        ldr     r1, =CCM_BASE
+	ldr     r0, =CSCR_BCLK_133MHZ
+	str 	r0, [r1, #CCM_CSCR_OFF]
+	
+	ldr	r0, = MPCTL0_266MHZ
+	str	r0, [r1, #CCM_MPCTL0_OFF]
+	
+	ldr 	r0, [r1,#CCM_CSCR_OFF]
+	orr	r0,r0, #CSCR_MPLL_RESTART
+	str	r0, [r1, #CCM_CSCR_OFF]
+
+mpll_restart_wait:
+        ldr     r1, =CCM_BASE
+	ldr	r0, [r1, #CCM_CSCR_OFF]
+	ands	r0,r0,#CSCR_MPLL_RESTART
+	bne	mpll_restart_wait
+
+mpll_lock_wait:
+        ldr     r1, =CCM_BASE
+	ldr	r0, [r1, #CCM_MPCTL1_OFF]
+	ands	r0,r0, #MPCTL1_LF
+	beq	mpll_lock_wait
+	
+	/* SPLL */
+	ldr	r0, =SPCTL0_288MHZ;
+	str	r0, [r1, #CCM_SPCTL0_OFF]
+
+	ldr	r0, [r1, #CCM_CSCR_OFF]
+	orr	r0, r0, #CSCR_SPLL_RESTART
+	str	r0, [r1, #CCM_CSCR_OFF]
+
+spll_restart_wait:
+        ldr     r1, =CCM_BASE
+	ldr	r0, [r1, #CCM_CSCR_OFF]
+	ands	r0, r0,#CSCR_SPLL_RESTART
+	bne	spll_restart_wait	
+
+spll_lock_wait:
+        ldr     r1, =CCM_BASE
+	ldr 	r0, [r1, #CCM_SPCTL1_OFF]	
+	ands	r0, r0, #SPCTL1_LF
+	beq	spll_lock_wait
+
+	 /* set BCLK to 133MHz, USBCLK to 48 MHz */
+
+        ldr     r1, =CCM_BASE
+        ldr     r0, =CSCR_BCLK_133MHZ
+	str	r0, [r1, #CCM_CSCR_OFF]
+
+	ldr 	r0, = (PCDR0_SSI2DIV(25)	| \
+                        PCDR0_SSI1DIV(25)	| \
+                        PCDR0_NFCDIV(4)		| \
+                        PCDR0_CLKO_48MDIV(1)	| \
+                        PCDR0_FIRIDIV(8))
+	str	r0, [r1, #CCM_PCDR0_OFF]
+
+
+        ldr     r1, =CCM_BASE
+        ldr	r0, = (PCDR1_PERDIV4(3)		| \
+                        PCDR1_PERDIV3(6)	| \
+                        PCDR1_PERDIV2(8)	| \
+                        PCDR1_PERDIV1(6))
+	str	r0, [r1, #CCM_PCDR1_OFF]
+
+	ldr	r0, =CCSR_CLKO_PERCLK1
+	str	r0, [r1, #CCM_CCSR_OFF]
+
+
+	/* enable clocks to various peripheral modules */
+        ldr     r0, =PCCR0_VAL
+        str     r0, [r1, #CCM_PCCR0_OFF]
+        ldr     r0, =PCCR1_VAL
+        str     r0, [r1, #CCM_PCCR1_OFF]
+
+
+	/* Init master priorities in AHB Crossbar switch */
+
+	ldr 	r1, = MAX_MPR_ADDR(3)
+	ldr	r0, = (	MAX_MPR_MSTR5(1) | \
+			MAX_MPR_MSTR4(2) | \
+			MAX_MPR_MSTR3(3) | \
+			MAX_MPR_MSTR2(0) | \
+			MAX_MPR_MSTR1(5) | \
+			MAX_MPR_MSTR0(6))
+	str	r0, [r1]
+
+        /*
+         * go to Asynchronous Bus mode
+         * set NotFast and iA bits
+         */
+        mrc     p15, 0, r0, c1, c0, 0
+        orr     r0, r0, #(3<<30)        @ set nF and iA bits
+        mcr     p15, 0, r0, c1, c0, 0
+        nop
+        nop
+        nop
+        nop
+        nop
+
+	/* enable user mode CSI access */
+        ldr     r1, =SYSCTL_GPCR
+        ldr     r0, [r1]
+        bic     r0, r0, #GPCR_CSI_PROTECT
+        str     r0, [r1]
+
+        /*
+         * allow all registers to be accessed in user-land.
+         * this allows /dev/mem to be accessed via mmap(2).
+         */
+        mov     r0, #0
+        ldr     r1, =AIPI0_PAR
+        str     r0, [r1]
+
+        ldr     r1, =AIPI1_PAR
+        str     r0, [r1]
+
+        /* CS0 Upper */
+        ldr     r1,=CS0U
+        ldr     r0,=0x00000A00  // 11 wait states
+        str     r0,[r1]
+
+        /* CS0 Lower */
+        ldr     r1,=CS0L
+        ldr     r0,=0x00000E01
+        str     r0,[r1]
+
+//comment # Setting for Memory Map IO Port
+//comment # CS1 Initialization (Async Mode)
+//comment # 16-bit, D0..15, ?? wait states
+//setmem 0xDF001008 0x00002000 32
+//setmem 0xDF00100C 0x11118501 32
+        ldr     r1,=CS1U
+        ldr     r0,=0x00002000
+        str     r0,[r1]
+
+        ldr     r1,=CS1L
+        ldr     r0,=0x11118501
+        str     r0,[r1]
+
+//comment # Config MUX for pin PF18->CS1
+//comment # Clear PTF_GIUSE
+//setmem 0x10015520 0x00000000 32
+//comment # Clear PTF_GPR
+//setmem 0x10015538 0x00000000 32
+
+
+        ldr     r1,=PTF_GIUS
+        ldr     r0, [r1]
+        bic     r0, r0, #(1 << 18)
+        str     r0,[r1]
+
+        ldr     r1,=PTF_GPR
+        ldr     r0, [r1]
+        bic     r0, r0, #(1 << 18)
+        str     r0,[r1]
+
+//comment # CS3 Initialization (Async Mode) SRAM on EVB Base Board
+//comment # 32-bit, ?? wait states
+//setmem 0xDF001018 0x00000E00 32
+//setmem 0xDF00101C 0x11110601 32
+        ldr     r1,=CS3U
+        ldr     r0,=0x00000E00
+        str     r0,[r1]
+
+        ldr     r1,=CS3L
+        ldr     r0,=0x11110601
+        str     r0,[r1]
+
+//comment # FMCR Register
+//comment # Select CS3/CSD0 Pin as CS3 only.
+//setmem 0x10027814 0xFFFFFFC9 32
+
+        ldr     r1,=SYSCTL_FMCR
+        ldr     r0,=0xFFFFFFC9
+        str     r0,[r1]
+
+
+        /*
+         *  Don't bother initializing SDRAM if we're already running in it.
+         *  This can happen as a result of a "reblob" command.
+         */
+        mov     r0, r5                  @ where we came from
+        ldr     r1, =0x08000000         @ see if were already running in sdram
+        ands    r0, r0, r1
+        moveq   pc, r5                  @ we are, just split
+
+	
+        /*
+         * Initialize SDRAM Controller
+         */
+        ldr     r1, =SDRC_SDCTL0
+        ldr     r0, =0x92120300         @ precharge command
+        str     r0, [r1]
+        ldr     r2, =0xC0200000         @ precharge all
+        ldr     r0, [r2]
+        bl      mem_delay
+
+	/* JEDEC 3.11.5.1-7: issue 8 or more autorefresh commands */
+
+        ldr     r0, =0xA2120300         @ auto-refresh command
+        str     r0, [r1]
+        ldr     r2, =0xC0000000         @ special read from SDRAM
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+        ldr     r0, [r2]
+
+	/* Set mode register command */
+        ldr     r0, =0xB2120300         @ set mode register
+        str     r0, [r1]
+
+	/* 
+ 	 * 0x119800 >> (9cols + 2) = 0x233
+	 *
+ 	 * Burst Length 	8 	(0x3) 
+	 * CAS Latency 		3 	(0x30)
+	 * Write Burst		enabled	(0x200)
+	 *  
+	 */
+        ldr     r2, =0xC0119800         @ mode register command
+        ldr     r0, [r2]
+        bl      mem_delay
+
+	/* Goto normal mode */
+        ldr     r0, =0x8212F339         @ CAS 3
+        str     r0, [r1]                @ set normal mode
+
+	/* led */
+	ldr     r0, =OBR_BASE
+        ldrh    r1, [r0]
+        orr     r1, r1, #(OBR_LED3_ON)                  /* start with LED 3 on */
+        bic     r1, r1, #(OBR_LED4_ON)                  /* start with LED 4 off */
+        strh    r1, [r0]
+
+        mov     pc, r5                  @ split
+
+
+/*
+ *  spin for a while.  we need to wait at least 200 usecs.
+ */
+mem_delay:
+        mov     r6, lr                  @ save return addr
+
+        mov     r4, #0x4000             @ way longer than 200 usec
+spin:   subs    r4, r4, #1
+        bne     spin
+
+        mov     pc, r6
+
diff -X linux/Documentation/dontdiff -Nur u-boot-1.1.4/board/mx21ads/Makefile u-boot-1.1.4.imx21/board/mx21ads/Makefile
--- u-boot-1.1.4/board/mx21ads/Makefile	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-1.1.4.imx21/board/mx21ads/Makefile	2006-05-03 15:12:45.000000000 +0200
@@ -0,0 +1,48 @@
+#
+# board/mx1ads/Makefile
+#
+# (c) Copyright 2004
+# Techware Information Technology, Inc.
+# http://www.techware.com.tw/
+#
+# Ming-Len Wu <[e-mail]>
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+
+include $(TOPDIR)/config.mk
+
+LIB	= lib$(BOARD).a
+
+OBJS	:= mx21ads.o flash.o
+SOBJS	:= lowlevel_init.o
+
+$(LIB):	$(OBJS) $(SOBJS)
+	$(AR) crv $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak .depend
+
+#########################################################################
+
+.depend:	Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
+		$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
+
+-include .depend
+
+#########################################################################
diff -X linux/Documentation/dontdiff -Nur u-boot-1.1.4/board/mx21ads/mx21ads.c u-boot-1.1.4.imx21/board/mx21ads/mx21ads.c
--- u-boot-1.1.4/board/mx21ads/mx21ads.c	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-1.1.4.imx21/board/mx21ads/mx21ads.c	2006-05-26 10:00:18.000000000 +0200
@@ -0,0 +1,60 @@
+/*
+ * board/mx1ads/mx1ads.c
+ *
+ * (C) Copyright 2004
+ * Techware Information Technology, Inc.
+ * http://www.techware.com.tw/
+ *
+ * (C) Copyright 2006 Jochen Karrer
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <asm/arch/imx21-regs.h>
+
+int board_init(void) {
+	DECLARE_GLOBAL_DATA_PTR; 
+	gd->bd->bi_arch_number = MACH_TYPE_MX2ADS;
+        gd->bd->bi_boot_params = 0xC0000100;    /* adress of boot parameters    */
+//       icache_enable();
+//       dcache_enable();
+	
+	return 0;
+}
+void
+show_boot_progress(int status)
+{
+#ifdef CONFIG_SILENT_CONSOLE
+        if( status == 8) {
+                if( getenv("silent") != NULL ) {
+//                       *(volatile unsigned long *)0x206080 &= ~1;
+//                       *(volatile unsigned long *)0x207080 &= ~1;
+                }
+        }
+#endif
+        return;
+}
+
+int 
+dram_init (void) {
+        DECLARE_GLOBAL_DATA_PTR;
+
+        gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+        gd->bd->bi_dram[0].size  = PHYS_SDRAM_1_SIZE;
+
+        return 0;
+}
diff -X linux/Documentation/dontdiff -Nur u-boot-1.1.4/board/mx21ads/u-boot.lds u-boot-1.1.4.imx21/board/mx21ads/u-boot.lds
--- u-boot-1.1.4/board/mx21ads/u-boot.lds	1970-01-01 01:00:00.000000000 +0100
+++ u-boot-1.1.4.imx21/board/mx21ads/u-boot.lds	2006-04-26 16:10:13.000000000 +0200
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, [e-mail].
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0xc8000000;
+
+	. = ALIGN(4);
+	.text      :
+	{
+		cpu/arm926ejs/start.o	(.text)
+		*(.text)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(.rodata) }
+
+	. = ALIGN(4);
+	.data : { *(.data) }
+
+	. = ALIGN(4);
+	.got : { *(.got) }
+
+	. = .;
+	__u_boot_cmd_start = .;
+	.