mx21.h

FreeScale imx21开发板Nand flash烧写程序

//# $1002_2000 to $1002_2FFF              #		
//#########################################		
#define SLCDC_BASE_ADDR	0x10022000	
#define SLCDC_DBADDR	(SLCDC_BASE_ADDR+0x00)	//  32bit slcdc data base addr
#define SLCDC_DBUF_SIZE	(SLCDC_BASE_ADDR+0x04)	//  32bit slcdc data buffer size high
#define SLCDC_CBADDR	(SLCDC_BASE_ADDR+0x08)	//  32bit slcdc cmd base addr high
#define SLCDC_CBUF_SIZE	(SLCDC_BASE_ADDR+0x0C)	//  32bit slcdc cmd buffer size high
#define SLCDC_CBUF_SSIZE	(SLCDC_BASE_ADDR+0x10)	//  32bit slcdc cmd string size
#define SLCDC_FIFO_CONFIG	(SLCDC_BASE_ADDR+0x14)	//  32bit slcdc fifo config reg
#define SLCDC_LCD_CONFIG	(SLCDC_BASE_ADDR+0x18)	//  32bit slcdc lcd controller config
#define SLCDC_LCD_TXCONFIG	(SLCDC_BASE_ADDR+0x1C)	//  32bit slcdc lcd transmit config reg
#define SLCDC_LCD_CTRL_STAT	(SLCDC_BASE_ADDR+0x20)	//  32bit slcdc lcd control/status reg
#define SLCDC_LCD_CLKCONFIG	(SLCDC_BASE_ADDR+0x24)	//  32bit slcdc lcd clock config reg
#define SLCDC_LCD_WR_DATA	(SLCDC_BASE_ADDR+0x28)	//  32bit slcdc lcd write data reg
		
		
		
		
		
//#########################################		
//# SAHARA                                #		
//# $1002_3000 to $1002_3FFF              #		
//#########################################		
#define SAHARA_BASE_ADDR	0x10023000	
		
//# CHA BASE ADDRESSES		
#define SAHARA_TOP	(SAHARA_BASE_ADDR+0x0000)	
#define SAHARA_AESA	(SAHARA_BASE_ADDR+0x0100)	
#define SAHARA_DESA	(SAHARA_BASE_ADDR+0x0101)	
#define SAHARA_MDHA	(SAHARA_BASE_ADDR+0x0200)	
#define SAHARA_RNGA	(SAHARA_BASE_ADDR+0x0300)	
#define SAHARA_FIDO	(SAHARA_BASE_ADDR+0x0400)	
#define SAHARA_I_FIDO	(SAHARA_BASE_ADDR+0x0400)	
#define SAHARA_O_FIDO	(SAHARA_BASE_ADDR+0x0500)	
#define SAHARA_PKHA	(SAHARA_BASE_ADDR+0x0800)	
		
//# SAHARA REGISTERS		
#define SAHARA_VER_ID	(SAHARA_TOP+0x00)	
#define SAHARA_DSC_ADR	(SAHARA_TOP+0x04)	
#define SAHARA_CONTROL	(SAHARA_TOP+0x08)	
#define SAHARA_COMMAND	(SAHARA_TOP+0x0C)	
#define SAHARA_STAT	(SAHARA_TOP+0x10)	
#define SAHARA_ERR_STAT	(SAHARA_TOP+0x14)	
#define SAHARA_FAULT_ADR	(SAHARA_TOP+0x18)	
#define SAHARA_C_DSC_ADR	(SAHARA_TOP+0x1C)	
#define SAHARA_I_DSC_ADR	(SAHARA_TOP+0x20)	
#define SAHARA_BUFF_LVL	(SAHARA_TOP+0x24)	
#define SAHARA_DSC_A	(SAHARA_TOP+0x80)	
#define SAHARA_DSC_B	(SAHARA_TOP+0x84)	
#define SAHARA_DSC_C	(SAHARA_TOP+0x88)	
#define SAHARA_DSC_D	(SAHARA_TOP+0x8C)	
#define SAHARA_DSC_E	(SAHARA_TOP+0x90)	
#define SAHARA_DSC_F	(SAHARA_TOP+0x94)	
#define SAHARA_LNK_1_A	(SAHARA_TOP+0xA0)	
#define SAHARA_LNK_1_B	(SAHARA_TOP+0xA4)	
#define SAHARA_LNK_1_C	(SAHARA_TOP+0xA8)	
#define SAHARA_LNK_2_A	(SAHARA_TOP+0xB0)	
#define SAHARA_LNK_2_B	(SAHARA_TOP+0xB4)	
#define SAHARA_LNK_2_C	(SAHARA_TOP+0xB8)	
#define SAHARA_FLOW_CTRL	(SAHARA_TOP+0xC0)	
		
//# COMMON CHA REGISTERS		
#define SAHARA_MODE	0x00	
#define SAHARA_KEY_SIZE	0x04	
#define SAHARA_DATA_SIZE	0x08	
#define SAHARA_STATUS	0x0C	
#define SAHARA_ERROR_STATUS	0x10	
#define SAHARA_CHA_GO	0x14	
#define SAHARA_CONTEXT	0x40	
#define SAHARA_KEY	0x80	
		
//# SAHARA_AESA REGISTERS		
#define SAHARA_AESA_MODE	(SAHARA_AESA+SAHARA_MODE+0x00)	
#define SAHARA_AESA_KEY_SIZE	(SAHARA_AESA+SAHARA_KEY_SIZE+0x00)	
#define SAHARA_AESA_DATA_SIZE	(SAHARA_AESA+SAHARA_DATA_SIZE+0x00)	
#define SAHARA_AESA_STAT	(SAHARA_AESA+SAHARA_STATUS+0x00)	
#define SAHARA_AESA_ERR_STAT	(SAHARA_AESA+SAHARA_ERROR_STATUS+0x00)	
#define SAHARA_AESA_CHA_GO	(SAHARA_AESA+SAHARA_CHA_GO+0x00)	
#define SAHARA_AESA_CXT	(SAHARA_AESA+SAHARA_CONTEXT+0x00)	
#define SAHARA_AESA_KEY_1	(SAHARA_AESA+SAHARA_KEY+0x00)	
#define SAHARA_AESA_KEY_2	(SAHARA_AESA+SAHARA_KEY+0x04)	
#define SAHARA_AESA_KEY_3	(SAHARA_AESA+SAHARA_KEY+0x08)	
#define SAHARA_AESA_KEY_4	(SAHARA_AESA+SAHARA_KEY+0x0C)	
#define SAHARA_AESA_IV_1	(SAHARA_AESA+SAHARA_CONTEXT+0x00)	
#define SAHARA_AESA_IV_2	(SAHARA_AESA+SAHARA_CONTEXT+0x04)	
#define SAHARA_AESA_IV_3	(SAHARA_AESA+SAHARA_CONTEXT+0x08)	
#define SAHARA_AESA_IV_4	(SAHARA_AESA+SAHARA_CONTEXT+0x0C)	
#define SAHARA_AESA_IV_5	(SAHARA_AESA+SAHARA_CONTEXT+0x10)	
#define SAHARA_AESA_IV_6	(SAHARA_AESA+SAHARA_CONTEXT+0x14)	
#define SAHARA_AESA_IV_7	(SAHARA_AESA+SAHARA_CONTEXT+0x18)	
#define SAHARA_AESA_IV_8	(SAHARA_AESA+SAHARA_CONTEXT+0x1C)	
#define SAHARA_AESA_IV_9	(SAHARA_AESA+SAHARA_CONTEXT+0x20)	
#define SAHARA_AESA_IV_10	(SAHARA_AESA+SAHARA_CONTEXT+0x24)	
#define SAHARA_AESA_IV_11	(SAHARA_AESA+SAHARA_CONTEXT+0x28)	
#define SAHARA_AESA_IV_12	(SAHARA_AESA+SAHARA_CONTEXT+0x2C)	
#define SAHARA_AESA_IV_13	(SAHARA_AESA+SAHARA_CONTEXT+0x30)	
#define SAHARA_AESA_IV_14	(SAHARA_AESA+SAHARA_CONTEXT+0x34)	
#define SAHARA_AESA_IV_15	(SAHARA_AESA+SAHARA_CONTEXT+0x38)	
#define SAHARA_AESA_IV_16	(SAHARA_AESA+SAHARA_CONTEXT+0x3C)	
		
//# SAHARA_DESA REGISTERS		
#define SAHARA_DESA_MODE	(SAHARA_DESA+SAHARA_MODE+0x00)	
#define SAHARA_DESA_KEY_SIZE	(SAHARA_DESA+SAHARA_KEY_SIZE+0x00)	
#define SAHARA_DESA_DATA_SIZE	(SAHARA_DESA+SAHARA_DATA_SIZE+0x00)	
#define SAHARA_DESA_STAT	(SAHARA_DESA+SAHARA_STATUS+0x00)	
#define SAHARA_DESA_ERR_STAT	(SAHARA_DESA+SAHARA_ERROR_STATUS+0x00)	
#define SAHARA_DESA_CHA_GO	(SAHARA_DESA+SAHARA_CHA_GO+0x00)	
#define SAHARA_DESA_KEY	(SAHARA_DESA+SAHARA_KEY+0x00)	
#define SAHARA_DESA_CXT	(SAHARA_DESA+SAHARA_CONTEXT+0x00)	
#define SAHARA_DESA_KEY_1	(SAHARA_DESA+SAHARA_KEY+0x00)	
#define SAHARA_DESA_KEY_2	(SAHARA_DESA+SAHARA_KEY+0x04)	
#define SAHARA_DESA_KEY_3	(SAHARA_DESA+SAHARA_KEY+0x08)	
#define SAHARA_DESA_KEY_4	(SAHARA_DESA+SAHARA_KEY+0x0C)	
#define SAHARA_DESA_KEY_5	(SAHARA_DESA+SAHARA_KEY+0x10)	
#define SAHARA_DESA_KEY_6	(SAHARA_DESA+SAHARA_KEY+0x14)	
#define SAHARA_DESA_IV_1	(SAHARA_DESA+SAHARA_CONTEXT+0x00)	
#define SAHARA_DESA_IV_2	(SAHARA_DESA+SAHARA_CONTEXT+0x04)	
		
//# SAHARA_MDHA REGISTERS		
#define SAHARA_MDHA_MODE	(SAHARA_MDHA+SAHARA_MODE+0x00)	
#define SAHARA_MDHA_KEY_SIZE	(SAHARA_MDHA+SAHARA_KEY_SIZE+0x00)	
#define SAHARA_MDHA_DATA_SIZE	(SAHARA_MDHA+SAHARA_DATA_SIZE+0x00)	
#define SAHARA_MDHA_STAT	(SAHARA_MDHA+SAHARA_STATUS+0x00)	
#define SAHARA_MDHA_ERR_STAT	(SAHARA_MDHA+SAHARA_ERROR_STATUS+0x00)	
#define SAHARA_MDHA_GO	(SAHARA_MDHA+SAHARA_CHA_GO+0x00)	
#define SAHARA_MDHA_KEY	(SAHARA_MDHA+SAHARA_KEY+0x00)	
#define SAHARA_MDHA_CXT	(SAHARA_MDHA+SAHARA_CONTEXT+0x00)	
#define SAHARA_MDHA_MD_A1	(SAHARA_MDHA+SAHARA_KEY+0x00)	
#define SAHARA_MDHA_MD_B1	(SAHARA_MDHA+SAHARA_KEY+0x04)	
#define SAHARA_MDHA_MD_C1	(SAHARA_MDHA+SAHARA_KEY+0x08)	
#define SAHARA_MDHA_MD_D1	(SAHARA_MDHA+SAHARA_KEY+0x0C)	
#define SAHARA_MDHA_MD_E1	(SAHARA_MDHA+SAHARA_KEY+0x10)	
#define SAHARA_MDHA_MD_A	(SAHARA_MDHA+SAHARA_CONTEXT+0x00)	
#define SAHARA_MDHA_MD_B	(SAHARA_MDHA+SAHARA_CONTEXT+0x04)	
#define SAHARA_MDHA_MD_C	(SAHARA_MDHA+SAHARA_CONTEXT+0x08)	
#define SAHARA_MDHA_MD_D	(SAHARA_MDHA+SAHARA_CONTEXT+0x0C)	
#define SAHARA_MDHA_MD_E	(SAHARA_MDHA+SAHARA_CONTEXT+0x10)	
#define SAHARA_MDHA_MD_CNT	(SAHARA_MDHA+SAHARA_CONTEXT+0x14)	
		
//# SAHARA_PKHA REGISTERS		
#define SAHARA_PKHA_PGM_COUNT	(SAHARA_PKHA+SAHARA_MODE+0x000)	
#define SAHARA_PKHA_KEY_SIZE	(SAHARA_PKHA+SAHARA_KEY_SIZE+0x000)	
#define SAHARA_PKHA_MOD_SIZE	(SAHARA_PKHA+SAHARA_DATA_SIZE+0x000)	
#define SAHARA_PKHA_STAT	(SAHARA_PKHA+SAHARA_STATUS+0x000)	
#define SAHARA_PKHA_ERR_STAT	(SAHARA_PKHA+SAHARA_ERROR_STATUS+0x000)	
#define SAHARA_PKHA_CHA_GO	(SAHARA_PKHA+SAHARA_CHA_GO+0x000)	
#define SAHARA_PKHA_A0_BASE	(SAHARA_PKHA+0x400)	
#define SAHARA_PKHA_A1_BASE	(SAHARA_PKHA+0x440)	
#define SAHARA_PKHA_A2_BASE	(SAHARA_PKHA+0x480)	
#define SAHARA_PKHA_A3_BASE	(SAHARA_PKHA+0x4C0)	
#define SAHARA_PKHA_B0_BASE	(SAHARA_PKHA+0x500)	
#define SAHARA_PKHA_B1_BASE	(SAHARA_PKHA+0x540)	
#define SAHARA_PKHA_B2_BASE	(SAHARA_PKHA+0x580)	
#define SAHARA_PKHA_B3_BASE	(SAHARA_PKHA+0x5C0)	
#define SAHARA_PKHA_N_BASE	(SAHARA_PKHA+0x600)	
#define SAHARA_PKHA_EXP_BASE	(SAHARA_PKHA+0x700)	
		
//# SAHARA_RNGA REGISTERS		
#define SAHARA_RNGA_MODE	(SAHARA_RNGA+SAHARA_MODE+0x00)	
#define SAHARA_RNGA_DATA_SIZE	(SAHARA_RNGA+SAHARA_DATA_SIZE+0x00)	
#define SAHARA_RNGA_STAT	(SAHARA_RNGA+SAHARA_STATUS+0x00)	
#define SAHARA_RNGA_ERR_STAT	(SAHARA_RNGA+SAHARA_ERROR_STATUS+0x00)	
#define SAHARA_RNGA_CHA_GO	(SAHARA_RNGA+SAHARA_CHA_GO+0x00)	
		
		
		
		
		
//#########################################		
//# USBOTG                                #		
//# $1002_4000 to $1002_5FFF              #		
//#########################################		
#define OTG_BASE_ADDR	0x10024000	
#define OTG_CORE_BASE	(OTG_BASE_ADDR+0x000)	//  base location for core
#define OTG_FUNC_BASE	(OTG_BASE_ADDR+0x040)	//  base location for function
#define OTG_HOST_BASE	(OTG_BASE_ADDR+0x080)	//  base location for host
#define OTG_DMA_BASE	(OTG_BASE_ADDR+0x800)	//  base location for dma
		
#define OTG_ETD_BASE	(OTG_BASE_ADDR+0x200)	//  base location for etd memory
#define OTG_EP_BASE	(OTG_BASE_ADDR+0x400)	//  base location for ep memory
#define OTG_SYS_BASE	(OTG_BASE_ADDR+0x600)	//  base location for system
#define OTG_DATA_BASE	(OTG_BASE_ADDR+0x1000)	//  base location for data memory

#define OTG_SYS_CTRL	(OTG_SYS_BASE+0x000)	//  base location for system
		
#define OTG_CORE_HWMODE	(OTG_CORE_BASE+0x00)	//  32bit core hardware mode reg
#define OTG_CORE_CINT_STAT	(OTG_CORE_BASE+0x04)	//  32bit core int status reg
#define OTG_CORE_CINT_STEN	(OTG_CORE_BASE+0x08)	//  32bit core int enable reg
#define OTG_CORE_CLK_CTRL	(OTG_CORE_BASE+0x0C)	//  32bit core clock control reg
#define OTG_CORE_RST_CTRL	(OTG_CORE_BASE+0x10)	//  32bit core reset control reg
#define OTG_CORE_FRM_INTVL	(OTG_CORE_BASE+0x14)	//  32bit core frame interval reg
#define OTG_CORE_FRM_REMAIN	(OTG_CORE_BASE+0x18)	//  32bit core frame remaining reg
#define OTG_CORE_HNP_CSTAT	(OTG_CORE_BASE+0x1C)	//  32bit core HNP current state reg
#define OTG_CORE_HNP_TIMER1	(OTG_CORE_BASE+0x20)	//  32bit core HNP timer 1 reg
#define OTG_CORE_HNP_TIMER2	(OTG_CORE_BASE+0x24)	//  32bit core HNP timer 2 reg
#define OTG_CORE_HNP_T3PCR	(OTG_CORE_BASE+0x28)	//  32bit core HNP timer 3 pulse ctrl
#define OTG_CORE_HINT_STAT	(OTG_CORE_BASE+0x2C)	//  32bit core HNP int status reg
#define OTG_CORE_HINT_STEN	(OTG_CORE_BASE+0x30)	//  32bit core HNP int enable reg
		
#define OTG_FUNC_CND_STAT	(OTG_FUNC_BASE+0x00)	//  32bit func command status reg
#define OTG_FUNC_DEV_ADDR	(OTG_FUNC_BASE+0x04)	//  32bit func device address reg
#define OTG_FUNC_SINT_STAT	(OTG_FUNC_BASE+0x08)	//  32bit func system int status reg
#define OTG_FUNC_SINT_STEN	(OTG_FUNC_BASE+0x0C)	//  32bit func system int enable reg
#define OTG_FUNC_XINT_STAT	(OTG_FUNC_BASE+0x10)	//  32bit func X buf int status reg
#define OTG_FUNC_YINT_STAT	(OTG_FUNC_BASE+0x14)	//  32bit func Y buf int status reg
#define OTG_FUNC_XYINT_STEN	(OTG_FUNC_BASE+0x18)	//  32bit func XY buf int enable reg
#define OTG_FUNC_XFILL_STAT	(OTG_FUNC_BASE+0x1C)	//  32bit func X filled status reg
#define OTG_FUNC_YFILL_STAT	(OTG_FUNC_BASE+0x20)	//  32bit func Y filled status reg
#define OTG_FUNC_EP_EN	(OTG_FUNC_BASE+0x24)	//  32bit func endpoints enable reg
#define OTG_FUNC_EP_RDY	(OTG_FUNC_BASE+0x28)	//  32bit func endpoints ready reg
#define OTG_FUNC_IINT	(OTG_FUNC_BASE+0x2C)	//  32bit func immediate interrupt reg
#define OTG_FUNC_EP_DSTAT	(OTG_FUNC_BASE+0x30)	//  32bit func endpoints done status
#define OTG_FUNC_EP_DEN	(OTG_FUNC_BASE+0x34)	//  32bit func endpoints done enable
#define OTG_FUNC_EP_TOGGLE	(OTG_FUNC_BASE+0x38)	//  32bit func endpoints toggle bits
#define OTG_FUNC_FRM_NUM	(OTG_FUNC_BASE+0x3C)	//  32bit func frame number reg
		
#define OTG_HOST_CTRL	(OTG_HOST_BASE+0x00)	//  32bi