📄 tht_memory_map_defines.h
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// This Is a generated file. Source is an Excel sheet. DO NOT EDIT
//############################################################################
//# #
//# Tahiti specific tht_memory_map.equ #
//# Motorola Confidential Proprietary #
//# Purpose: #
//# This file is used by the ARM ADS assembler to decode the memory map #
//# #
//# Description #
//# This file list out each individual memory location for decoding #
//# #
//# Initial version writen By #
//# JM Kam (jmkam@motorola.com) SPS/WBSG SNP #
//# #
//# Date #
//# 13 Jan 2003 #
//# #
//# Status #
//# clock rest module: Added sys control registsers temporarily #
//# Chapters Missing: HAB EMMA DEC EMMA ENC #
//# #
//# Revisions #
//# Date By Description of changes #
//# 20 Nov 2002 JM Kam Initial release for Tahiti IC Spec 0.3 #
//# 21 Dec 2002 JM Kam Changed over to Tahiti-Lite IC Spec 0.1 #
//# - filled in SCM SMN ROMPATCH SLCDC AUDMUX #
//# - renamed EIM to WEIM #
//# - updated DMA CCM LCDC EMMA RTC WDOG #
//# PWM UART FIRI GPIO #
//# - temp allocated AIPI1 en 22 to AUDMUX #
//# 17 Jan 2003 JM Kam Changed over to Tahiti-Lite IC Spec 0.2 #
//# - Additions for CRM NFC BMI EMMA SSI #
//# PCMCIA GPIO USBOTG BMI SAHARA #
//# - Split system control regs away from CRM #
//# - left in CRM reg space and tagged SYS #
//# Corrections for (from v0.1) #
//# -CRM FIRI SLCDC LCDC #
//# Confirm allocated AIPI1 en 22 to AUDMUX #
//# 14 Feb 2003 JM Kam Emma memory map updated for end and dec #
//# Added new registers for DMA module #
//# 19 Feb 2003 JM Kam Added one register for CSI CSIRXCNT #
//# 20 Feb 2003 JM Kam Added LCDC_LIER and LCDC_LGWDCS #
//# #
//############################################################################
//Memory Map
//----------
//$0000_0000 - $0000_3FFF BROM ()
//$0000_4000 - $0040_3FFF reserved
//$0040_4000 - $007F_FFFF BROM ()
//$0080_0000 - $0FFF_FFFF reserved
//$1000_0000 - $1000_0FFF AIPI1 ()
//$1000_1000 - $1000_1FFF DMA ()
//$1000_2000 - $1000_2FFF WDOG ()
//$1000_3000 - $1000_3FFF GPT1 ()
//$1000_4000 - $1000_4FFF GPT2 ()
//$1000_5000 - $1000_5FFF GPT3 ()
//$1000_6000 - $1000_6FFF PWM ()
//$1000_7000 - $1000_7FFF RTC ()
//$1000_8000 - $1000_8FFF KPP ()
//$1000_9000 - $1000_9FFF OWIRE ()
//$1000_A000 - $1000_AFFF UART1 ()
//$1000_B000 - $1000_BFFF UART2 ()
//$1000_C000 - $1000_CFFF UART3 ()
//$1000_D000 - $1000_DFFF UART4 ()
//$1000_E000 - $1000_EFFF CSPI1 ()
//$1000_F000 - $1000_FFFF CSPI2 ()
//$1001_0000 - $1001_0FFF SSI1 ()
//$1001_1000 - $1001_1FFF SSI2 ()
//$1001_2000 - $1001_2FFF I2C ()
//$1001_3000 - $1001_3FFF SDHC1 ()
//$1001_4000 - $1001_4FFF SDHC2 ()
//$1001_5000 - $1001_5FFF GPIO ()
//$1001_6000 - $1001_6FFF AUDMUX ()
//$1001_7000 - $1001_7FFF reserved
//$1001_8000 - $1001_8FFF reserved
//$1001_9000 - $1001_9FFF reserved
//$1001_A000 - $1001_AFFF reserved
//$1001_B000 - $1001_BFFF reserved
//$1001_C000 - $1001_CFFF reserved
//$1001_D000 - $1001_DFFF reserved
//$1001_E000 - $1001_EFFF reserved
//$1001_F000 - $1001_FFFF reserved
//$1002_0000 - $1002_0FFF AIPI2 ()
//$1002_1000 - $1002_1FFF LCDC ()
//$1002_2000 - $1002_2FFF SLCDC ()
//$1002_4000 - $1002_4FFF USBOTG ()
//$1002_5000 - $1002_5FFF USBOTG ()
//$1002_6000 - $1002_6FFF EMMA ()
//$1002_7000 - $1002_7FFF CRM and SYS ()
//$1002_8000 - $1002_8FFF FIRI ()
//$1002_9000 - $1002_9FFF reserved
//$1002_A000 - $1002_AFFF reserved
//$1002_B000 - $1002_BFFF reserved
//$1002_C000 - $1002_CFFF reserved
//$1002_D000 - $1002_DFFF reserved
//$1002_E000 - $1002_EFFF reserved
//$1003_0000 - $1003_0FFF reserved
//$1003_1000 - $1003_1FFF reserved
//$1003_2000 - $1003_2FFF reserved
//$1003_3000 - $1003_3FFF reserved
//$1003_5000 - $1003_5FFF reserved
//$1003_6000 - $1003_6FFF reserved
//$1003_7000 - $1003_7FFF reserved
//$1003_8000 - $1003_8FFF reserved
//$1003_9000 - $1003_9FFF reserved
//$1003_A000 - $1003_AFFF reserved
//$1003_B000 - $1003_BFFF reserved
//$1003_C000 - $1003_CFFF reserved
//$1003_D000 - $1003_DFFF reserved
//$1003_E000 - $1003_EFFF JAM ()
//$1003_F000 - $1003_FFFF MAX ()
//$1004_0000 - $1004_0FFF AITC ()
//$1004_1000 - $1004_1FFF ROMPATCH ()
//$1004_2000 - $1004_2FFF SMN ()
//$1004_3000 - $1004_3FFF SCM ()
//$1004_4000 - $7FFF_FFFF reserved
//$8000_0000 - $8000_0FFF CSI ()
//$8000_1000 - $9FFF_FFFF reserved
//$A000_0000 - $A000_0FFF BMI ()
//$A000_1000 - $BFFF_FFFF reserved
//$C000_0000 - $C3FF_FFFF External Memory (CSD0)
//$C400_0000 - $C7FF_FFFF External Memory (CSD1)
//$C800_0000 - $CBFF_FFFF External Memory (CS0)
//$CC00_0000 - $CFFF_FFFF External Memory (CS1)
//$D000_0000 - $D0FF_FFFF External Memory (CS2)
//$D100_0000 - $D1FF_FFFF External Memory (CS3)
//$D200_0000 - $D2FF_FFFF External Memory (CS4)
//$D300_0000 - $D3FF_FFFF External Memory (CS5)
//$D400_0000 - $D7FF_FFFF External Memory (PCMCIA/CF)
//$D800_0000 - $DEFF_FFFF reserved
//$DF00_0000 - $DF00_0FFF SDRAMC
//$DF00_1000 - $DF00_1FFF WEIM
//$DF00_2000 - $DF00_2FFF PCMCIA
//$DF00_3000 - $DF00_3FFF NFC
//$DF00_4000 - $DFFF_FFFF reserved
//$E000_0000 - $FFFF_FEFF reserved
//$FFFF_FF00 - $FFFF_FFFF VRAM
//#########################################
//# BOOT ROM #
//# $0000_0000 to $0000_3FFF #
//# $0040_4000 to $007F_FFFF #
//#########################################
#define BOOTROM1_ADDR_BOT 0x00000000 // boot rom section 1 bottom address
#define BOOTROM1_PHY_SIZE 0x00004000 // boot rom section 1 physical size
#define BOOTROM1_ASS_SIZE 0x00004000 // boot rom section 1 assigned size
#define BOOTROM2_ADDR_BOT 0x00404000 // boot rom section 2 bottom address
#define BOOTROM2_PHY_SIZE 0x003F4000 // boot rom section 2 physical size
#define BOOTROM2_ASS_SIZE 0x003F4000 // boot rom section 2 assigned size
//#########################################
//# AIPI1 #
//# $1000_0000 to $1000_0FFF #
//#########################################
#define AIPI1_BASE_ADDR 0x10000000
#define AIPI1_PSR0 (AIPI1_BASE_ADDR+0x00) // 32bit Peripheral Size Reg 0
#define AIPI1_PSR1 (AIPI1_BASE_ADDR+0x04) // 32bit Peripheral Size Reg 1
#define AIPI1_PAR (AIPI1_BASE_ADDR+0x08) // 32bit Peripheral Access Reg
//#########################################
//# DMA #
//# $1000_1000 to $1000_1FFF #
//#########################################
#define DMA_BASE_ADDR 0x10001000
#define DMA_SYS_BASE (DMA_BASE_ADDR+0x000) // base location for system
#define DMA_M2D_BASE (DMA_BASE_ADDR+0x040) // base location for 2D memory reg
#define DMA_CH0_BASE (DMA_BASE_ADDR+0x080) // base location for channel 0
#define DMA_CH1_BASE (DMA_BASE_ADDR+0x0C0) // base location for channel 1
#define DMA_CH2_BASE (DMA_BASE_ADDR+0x100) // base location for channel 2
#define DMA_CH3_BASE (DMA_BASE_ADDR+0x140) // base location for channel 3
#define DMA_CH4_BASE (DMA_BASE_ADDR+0x180) // base location for channel 4
#define DMA_CH5_BASE (DMA_BASE_ADDR+0x1C0) // base location for channel 5
#define DMA_CH6_BASE (DMA_BASE_ADDR+0x200) // base location for channel 6
#define DMA_CH7_BASE (DMA_BASE_ADDR+0x240) // base location for channel 7
#define DMA_CH8_BASE (DMA_BASE_ADDR+0x280) // base location for channel 8
#define DMA_CH9_BASE (DMA_BASE_ADDR+0x2C0) // base location for channel 9
#define DMA_CH10_BASE (DMA_BASE_ADDR+0x300) // base location for channel 10
#define DMA_CH11_BASE (DMA_BASE_ADDR+0x340) // base location for channel 11
#define DMA_CH12_BASE (DMA_BASE_ADDR+0x380) // base location for channel 12
#define DMA_CH13_BASE (DMA_BASE_ADDR+0x3C0) // base location for channel 13
#define DMA_CH14_BASE (DMA_BASE_ADDR+0x400) // base location for channel 14
#define DMA_CH15_BASE (DMA_BASE_ADDR+0x440) // base location for channel 15
#define DMA_TEST_BASE (DMA_BASE_ADDR+0x480) // base location for test registers
#define DMA_DCR (DMA_SYS_BASE+0x000) // 32bit dma control reg
#define DMA_DISR (DMA_SYS_BASE+0x004) // 32bit dma interrupt status reg
#define DMA_DIMR (DMA_SYS_BASE+0x008) // 32bit dma interrupt mask reg
#define DMA_DBTOSR (DMA_SYS_BASE+0x00C) // 32bit dma burst timeout stat reg
#define DMA_DRTOSR (DMA_SYS_BASE+0x010) // 32bit dma req timeout status reg
#define DMA_DSESR (DMA_SYS_BASE+0x014) // 32bit dma transfer err status reg
#define DMA_DBOSR (DMA_SYS_BASE+0x018) // 32bit dma buffer overflow stat reg
#define DMA_DBTOCR (DMA_SYS_BASE+0x01C) // 32bit dma burst timeout ctrl reg
#define DMA_WSRA (DMA_M2D_BASE+0x000) // 32bit dma W-size A reg
#define DMA_XSRA (DMA_M2D_BASE+0x004) // 32bit dma X-size A reg
#define DMA_YSRA (DMA_M2D_BASE+0x008) // 32bit dma Y-size A reg
#define DMA_WSRB (DMA_M2D_BASE+0x00C) // 32bit dma W-size B reg
#define DMA_XSRB (DMA_M2D_BASE+0x010) // 32bit dma X-size B reg
#define DMA_YSRB (DMA_M2D_BASE+0x014) // 32bit dma Y-size B reg
#define DMA_SAR0 (DMA_CH0_BASE+0x000) // 32bit dma ch0 source addr reg
#define DMA_DAR0 (DMA_CH0_BASE+0x004) // 32bit dma ch0 dest addr reg
#define DMA_CNTR0 (DMA_CH0_BASE+0x008) // 32bit dma ch0 count reg
#define DMA_CCR0 (DMA_CH0_BASE+0x00C) // 32bit dma ch0 control reg
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