📄 codec_edma.asm
字号:
NOP 3
RL2: ; CALL OCCURS ; |72|
ZERO .D2 B4 ; |83|
|| MVKL .S2 0x18c0008,B5 ; |83|
MVKH .S2 0x18c0008,B5 ; |83|
STW .D2T2 B4,*B5 ; |83|
MVKL .S1 0x18c0024,A0 ; |84|
MVKH .S1 0x18c0024,A0 ; |84|
STW .D1T2 B4,*A0 ; |84|
MVKL .S1 0x18c000c,A3 ; |85|
MVKL .S1 0x10040,A0 ; |85|
MVKH .S1 0x10040,A0 ; |85|
MVKH .S1 0x18c000c,A3 ; |85|
STW .D1T1 A0,*A3 ; |85|
MVKL .S2 0x18c0010,B5 ; |86|
MVKH .S2 0x18c0010,B5 ; |86|
STW .D2T1 A0,*B5 ; |86|
MVKL .S2 0x18c0004,B5 ; |87|
MVKH .S2 0x18c0004,B5 ; |87|
STW .D2T2 B4,*B5 ; |87|
MVKL .S2 0x12001,B4 ; |88|
|| MVKL .S1 0x18c0008,A0 ; |88|
MVKH .S2 0x12001,B4 ; |88|
|| MVKH .S1 0x18c0008,A0 ; |88|
STW .D1T2 B4,*A0 ; |88|
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;* Disqualified loop: bad loop structure
;*----------------------------------------------------------------------------*
L4:
;** -----------------------g5:
;** 75 ----------------------- goto g5;
.line 52
B .S1 L4 ; |75|
NOP 5
; BRANCH OCCURS ; |75|
;** --------------------------------------------------------------------------*
.endfunc 78,000080000h,8
.sect ".text"
.global _edma_isr
.sym _edma_isr,_edma_isr, 32, 2, 0
.func 141
;******************************************************************************
;* FUNCTION NAME: _edma_isr *
;* *
;* Regs Modified : A0,A1,A3,B0,B4,B5,B6,B7,B8,SP *
;* Regs Used : A0,A1,A3,B0,B4,B5,B6,B7,B8,DP,SP *
;* Local Frame Size : 0 Args + 0 Auto + 36 Save = 36 byte *
;******************************************************************************
_edma_isr:
;** --------------------------------------------------------------------------*
.line 2
.sym C$1,0, 19, 4, 32
.sym C$2,0, 19, 4, 32
.sym C$3,20, 4, 4, 32
.sym L$1,0, 4, 4, 32
.sym U$13,20, 4, 4, 32
.sym K$24,21, 4, 4, 32
.sym U$12,21, 4, 4, 32
.sym U$9,22, 4, 4, 32
.sym U$6,23, 4, 4, 32
;** 144 ----------------------- if ( (C$3 = dma_index) == 17 ) goto g2;
STW .D2T2 B8,*SP--(40) ; |142|
STW .D2T1 A0,*+SP(8) ; |142|
STW .D2T1 A1,*+SP(12) ; |142|
STW .D2T1 A3,*+SP(16) ; |142|
STW .D2T2 B0,*+SP(20) ; |142|
STW .D2T2 B4,*+SP(24) ; |142|
STW .D2T2 B5,*+SP(28) ; |142|
STW .D2T2 B6,*+SP(32) ; |142|
STW .D2T2 B7,*+SP(36) ; |142|
.line 4
LDW .D2T2 *+DP(_dma_index),B4 ; |144|
MVK .S2 17,B5 ; |144|
NOP 3
CMPEQ .L2 B4,B5,B0 ; |144|
[ B0] B .S1 L5 ; |144|
NOP 5
; BRANCH OCCURS ; |144|
;** --------------------------------------------------------------------------*
;** 152 ----------------------- dma_index = C$3+1;
;** 153 ----------------------- src = U$6 = src+160;
;** 154 ----------------------- dst = U$9 = dst+160;
;** ----------------------- U$12 = pcm_in;
;** ----------------------- U$13 = pcm_out;
;** 154 ----------------------- goto g3;
.line 12
ADD .D2 1,B4,B4 ; |152|
STW .D2T2 B4,*+DP(_dma_index) ; |152|
.line 13
LDW .D2T2 *+DP(_src),B4 ; |153|
MVK .S1 160,A0 ; |153|
NOP 3
ADD .S2X A0,B4,B7 ; |153|
STW .D2T2 B7,*+DP(_src) ; |153|
.line 14
LDW .D2T2 *+DP(_dst),B4 ; |154|
B .S1 L6 ; |154|
LDW .D2T2 *+DP(_pcm_in),B5
MVK .S2 160,B6 ; |154|
NOP 1
LDW .D2T2 *+DP(_pcm_out),B4
|| ADD .S2 B6,B4,B6 ; |154|
STW .D2T2 B6,*+DP(_dst) ; |154|
; BRANCH OCCURS ; |154|
;** --------------------------------------------------------------------------*
L5:
;** -----------------------g2:
;** 146 ----------------------- dma_index = 0;
;** 147 ----------------------- dst = U$9 = U$12 = pcm_in;
;** 148 ----------------------- src = U$6 = U$13 = pcm_out;
.line 6
ZERO .D2 B4 ; |146|
STW .D2T2 B4,*+DP(_dma_index) ; |146|
.line 7
LDW .D2T2 *+DP(_pcm_in),B5 ; |147|
NOP 4
MV .D2 B5,B6 ; |147|
STW .D2T2 B6,*+DP(_dst) ; |147|
.line 8
LDW .D2T2 *+DP(_pcm_out),B4 ; |148|
NOP 4
MV .D2 B4,B7 ; |148|
STW .D2T2 B7,*+DP(_src) ; |148|
;** --------------------------------------------------------------------------*
L6:
;** -----------------------g3:
;** 157 ----------------------- *(volatile unsigned *)0x1a0ffe4u = *(volatile unsigned *)0x1a0ffe4u|0x100u;
;** 158 ----------------------- *(volatile unsigned *)0x1a00184u = U$6;
;** 159 ----------------------- *(volatile unsigned *)0x1a001a4u = U$9;
;** 162 ----------------------- if ( (int)in_ptr-U$12 < 2880 ) goto g5;
;** 164 ----------------------- in_ptr = (short *)U$12;
;** -----------------------g5:
;** 168 ----------------------- if ( (int)out_ptr-U$13+(K$24 = (-2880)) < 0 ) goto g7;
;** 170 ----------------------- out_ptr = (short *)U$13;
;** -----------------------g7:
;** 173 ----------------------- L$1 = 80;
;** ----------------------- #pragma MUST_ITERATE(80, 80, 80)
;** -----------------------g9:
;** 173 ----------------------- C$1 = in_ptr;
;** 173 ----------------------- C$2 = out_ptr;
;** 173 ----------------------- *C$2 = *C$1&0xfffffffe;
;** 173 ----------------------- out_ptr = &C$2[1];
;** 173 ----------------------- in_ptr = &C$1[1];
;** 173 ----------------------- if ( --L$1 ) goto g9;
.line 17
MVKL .S1 0x1a0ffe4,A0 ; |157|
MVKH .S1 0x1a0ffe4,A0 ; |157|
LDW .D1T1 *A0,A0 ; |157|
MVKL .S2 0x1a0ffe4,B8 ; |157|
MVKH .S2 0x1a0ffe4,B8 ; |157|
NOP 2
SET .S1 A0,8,8,A0 ; |157|
STW .D2T1 A0,*B8 ; |157|
.line 18
MVKL .S2 0x1a00184,B8 ; |158|
MVKH .S2 0x1a00184,B8 ; |158|
STW .D2T2 B7,*B8 ; |158|
.line 19
MVKL .S2 0x1a001a4,B7 ; |159|
MVKH .S2 0x1a001a4,B7 ; |159|
STW .D2T2 B6,*B7 ; |159|
.line 22
LDW .D2T2 *+DP(_in_ptr),B6 ; |162|
MVK .S1 2880,A0 ; |162|
NOP 3
SUB .D2 B6,B5,B6 ; |162|
CMPLT .L1X B6,A0,A1 ; |162|
.line 24
[!A1] STW .D2T2 B5,*+DP(_in_ptr) ; |164|
.line 28
LDW .D2T2 *+DP(_out_ptr),B5 ; |168|
MVK .S2 0xfffff4c0,B6 ; |168|
NOP 3
SUB .D2 B5,B4,B5 ; |168|
ADD .D2 B6,B5,B5 ; |168|
CMPLT .L2 B5,0,B0 ; |168|
.line 30
[!B0] STW .D2T2 B4,*+DP(_out_ptr) ; |170|
.line 33
MVK .S1 0x50,A0 ; |173|
MVK .S1 0x1,A1 ; init prolog collapse predicate
|| MV .L2X A0,B0
|| MVC .S2 CSR,B5
AND .S2 -2,B5,B4
MVC .S2 B4,CSR ; interrupts off
;*----------------------------------------------------------------------------*
;* SOFTWARE PIPELINE INFORMATION
;*
;* Loop source line : 173
;* Loop opening brace source line : 173
;* Loop closing brace source line : 173
;* Known Minimum Trip Count : 80
;* Known Maximum Trip Count : 80
;* Known Max Trip Count Factor : 80
;* Loop Carried Dependency Bound(^) : 8
;* Unpartitioned Resource Bound : 3
;* Partitioned Resource Bound(*) : 5
;* Resource Partition:
;* A-side B-side
;* .L units 0 0
;* .S units 0 1
;* .D units 1 5*
;* .M units 0 0
;* .X cross paths 3 0
;* .T address paths 3 3
;* Long read paths 3 0
;* Long write paths 0 0
;* Logical ops (.LS) 3 1 (.L or .S unit)
;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
;* Bound(.L .S .LS) 2 1
;* Bound(.L .S .D .LS .LSD) 2 3
;*
;* Searching for software pipeline schedule at ...
;* ii = 8 Schedule found with 2 iterations in parallel
;* done
;*
;* Epilog not removed
;* Collapsed epilog stages : 0
;* Collapsed prolog stages : 1
;* Minimum required memory pad : 0 bytes
;*
;* Minimum safe trip count : 1
;*----------------------------------------------------------------------------*
L7: ; PIPED LOOP PROLOG
;** --------------------------------------------------------------------------*
L8: ; PIPED LOOP KERNEL
ADD .S1X 2,B4,A0 ; |173|
|| [!A1] LDH .D2T2 *B4,B4 ; ^ |173|
[ B0] SUB .S2 B0,1,B0 ; |173|
|| [!A1] STW .D2T1 A0,*+DP(_in_ptr) ; |173|
[ B0] B .S2 L8 ; |173|
LDW .D2T2 *+DP(_in_ptr),B4 ; @|173|
MV .S1X B4,A3 ; ^ Define a twin register
ADD .D1 2,A3,A0 ; ^ |173|
|| AND .S2 -2,B4,B4 ; ^ |173|
[!A1] STW .D2T1 A0,*+DP(_out_ptr) ; ^ |173|
|| MV .S1X B4,A0 ; ^ Define a twin register
[ A1] SUB .S1 A1,1,A1 ;
|| [!A1] STH .D1T1 A0,*A3 ; ^ |173|
|| LDW .D2T2 *+DP(_out_ptr),B4 ; @ ^ |173|
;** --------------------------------------------------------------------------*
L9: ; PIPED LOOP EPILOG
;** 177 ----------------------- in_ptr = in_ptr+160;
;** 178 ----------------------- out_ptr = out_ptr+160;
;** 178 ----------------------- return;
ADD .S1X 2,B4,A0 ; (E) @|173|
|| LDH .D2T2 *B4,B4 ; (E) @ ^ |173|
STW .D2T1 A0,*+DP(_in_ptr) ; (E) @|173|
NOP 2
MV .S1X B4,A3 ; (E) @ ^ Define a twin register
ADD .D1 2,A3,A0 ; (E) @ ^ |173|
|| AND .S2 -2,B4,B4 ; (E) @ ^ |173|
MV .S1X B4,A0 ; (E) @ ^ Define a twin register
|| STW .D2T1 A0,*+DP(_out_ptr) ; (E) @ ^ |173|
MVC .S2 B5,CSR ; interrupts on
|| STH .D1T1 A0,*A3 ; (E) @ ^ |173|
.line 37
NOP 1
LDW .D2T1 *+DP(_in_ptr),A0 ; |177|
NOP 4
ADDK .S1 160,A0 ; |177|
STW .D2T1 A0,*+DP(_in_ptr) ; |177|
.line 38
LDW .D2T2 *+DP(_out_ptr),B4 ; |178|
NOP 4
ADDK .S2 160,B4 ; |178|
STW .D2T2 B4,*+DP(_out_ptr) ; |178|
.line 40
LDW .D2T1 *+SP(8),A0 ; |180|
LDW .D2T1 *+SP(16),A3 ; |180|
LDW .D2T2 *+SP(24),B4 ; |180|
LDW .D2T2 *+SP(36),B7 ; |180|
LDW .D2T2 *+SP(28),B5 ; |180|
LDW .D2T2 *+SP(32),B6 ; |180|
LDW .D2T2 *+SP(20),B0 ; |180|
LDW .D2T1 *+SP(12),A1 ; |180|
|| B .S2 IRP ; |180|
LDW .D2T2 *++SP(40),B8 ; |180|
NOP 4
; BRANCH OCCURS ; |180|
.endfunc 180,001f1000bh,40
;; Inlined function references:
;; [ 6] mcbsp0_init
;******************************************************************************
;* TYPE INFORMATION *
;******************************************************************************
.stag $$fake1, 32
.member _INTSEL4, 0, 14, 18, 5
.member _INTSEL5, 5, 14, 18, 5
.member _INTSEL6, 10, 14, 18, 5
.member _rsvbit15, 15, 14, 18, 1
.member _INTSEL7, 16, 14, 18, 5
.member _INTSEL8, 21, 14, 18, 5
.member _INTSEL9, 26, 14, 18, 5
.member _rsvbit31, 31, 14, 18, 1
.eos
.utag $$fake0, 32
.member _exp, 0, 8, 11, 32, $$fake1
.member _reg, 0, 14, 11, 32
.eos
.stag $$fake3, 32
.member _INTSEL10, 0, 14, 18, 5
.member _INTSEL11, 5, 14, 18, 5
.member _INTSEL12, 10, 14, 18, 5
.member _rsvbit15, 15, 14, 18, 1
.member _INTSEL13, 16, 14, 18, 5
.member _INTSEL14, 21, 14, 18, 5
.member _INTSEL15, 26, 14, 18, 5
.member _rsvbit31, 31, 14, 18, 1
.eos
.utag $$fake2, 32
.member _reg, 0, 14, 11, 32
.member _exp, 0, 8, 11, 32, $$fake3
.eos
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