📄 flc3_samplea.mdl
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Position [200, 90, 225, 120]
}
Block {
BlockType SubSystem
Name "Fuzzy Subsystem"
Ports [2, 1]
Position [245, 65, 290, 105]
BackgroundColor "green"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Fuzzy Subsystem"
Location [281, 330, 751, 500]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [25, 33, 55, 47]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "In2"
Position [25, 68, 55, 82]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType SubSystem
Name "Fuzzy Subsystem 1"
Ports [2, 1]
Position [200, 28, 245, 77]
BackgroundColor "cyan"
TreatAsAtomicUnit off
MinAlgLoopOccurrences off
RTWSystemCode "Auto"
System {
Name "Fuzzy Subsystem 1"
Location [337, 370, 712, 487]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "white"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "A4"
PaperUnits "centimeters"
ZoomFactor "100"
Block {
BlockType Inport
Name "In1"
Position [60, 33, 90, 47]
Port "1"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Inport
Name "In2"
Position [60, 68, 90, 82]
Port "2"
IconDisplay "Port number"
LatchInput off
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [235, 26, 295, 74]
BackgroundColor "magenta"
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
ShowPortLabels on
fis "flc2_sample"
}
Block {
BlockType Mux
Name "Mux1"
Ports [2, 1]
Position [210, 31, 215, 69]
BackgroundColor "magenta"
ShowName off
Inputs "2"
DisplayOption "bar"
}
Block {
BlockType Saturate
Name "Saturation"
Position [155, 15, 185, 45]
BackgroundColor "magenta"
UpperLimit "2"
LowerLimit "-2"
}
Block {
BlockType Saturate
Name "Saturation1"
Position [155, 60, 185, 90]
BackgroundColor "magenta"
UpperLimit "1"
LowerLimit "-1"
}
Block {
BlockType Outport
Name "Out1"
Position [320, 43, 350, 57]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Mux1"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
}
Line {
SrcBlock "In2"
SrcPort 1
DstBlock "Saturation1"
DstPort 1
}
Line {
SrcBlock "Saturation"
SrcPort 1
Points [0, 10]
DstBlock "Mux1"
DstPort 1
}
Line {
SrcBlock "Saturation1"
SrcPort 1
Points [5, 0]
DstBlock "Mux1"
DstPort 2
}
Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "In1"
SrcPort 1
Points [45, 0]
DstBlock "Saturation"
DstPort 1
}
}
}
Block {
BlockType Gain
Name "Gain1"
Position [130, 25, 160, 55]
BackgroundColor "green"
Gain "SE"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain2"
Position [135, 61, 180, 89]
BackgroundColor "green"
Gain "SDE"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain3"
Position [260, 40, 290, 70]
BackgroundColor "green"
Gain "SU"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain4"
Position [135, 96, 180, 124]
BackgroundColor "green"
Gain "SI"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Integrator
Name "Integrator"
Ports [1, 1]
Position [230, 95, 260, 125]
IgnoreLimit off
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [325, 45, 345, 65]
ShowName off
IconShape "round"
}
Block {
BlockType Outport
Name "Out1"
Position [385, 48, 415, 62]
IconDisplay "Port number"
BusOutputAsStruct off
}
Line {
SrcBlock "Gain1"
SrcPort 1
DstBlock "Fuzzy Subsystem 1"
DstPort 1
}
Line {
SrcBlock "Gain2"
SrcPort 1
DstBlock "Fuzzy Subsystem 1"
DstPort 2
}
Line {
SrcBlock "In1"
SrcPort 1
Points [45, 0]
Branch {
DstBlock "Gain1"
DstPort 1
}
Branch {
Points [0, 70]
DstBlock "Gain4"
DstPort 1
}
}
Line {
SrcBlock "In2"
SrcPort 1
DstBlock "Gain2"
DstPort 1
}
Line {
SrcBlock "Fuzzy Subsystem 1"
SrcPort 1
DstBlock "Gain3"
DstPort 1
}
Line {
SrcBlock "Gain3"
SrcPort 1
Points [5, 0; 0, -30; 35, 0]
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Gain4"
SrcPort 1
DstBlock "Integrator"
DstPort 1
}
Line {
SrcBlock "Integrator"
SrcPort 1
Points [70, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
}
}
Block {
BlockType Gain
Name "Gain"
Position [95, 70, 125, 100]
Gain "2"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Gain
Name "Gain4"
Position [155, 25, 185, 55]
BackgroundColor "green"
Gain "SA"
ParameterDataTypeMode "Inherit via internal rule"
OutDataTypeMode "Inherit via internal rule"
SaturateOnIntegerOverflow off
}
Block {
BlockType Mux
Name "Mux"
Ports [3, 1]
Position [295, 146, 300, 184]
ShowName off
Inputs "3"
DisplayOption "bar"
}
Block {
BlockType DiscretePulseGenerator
Name "Pulse\nGenerator"
Ports [0, 1]
Position [20, 70, 50, 100]
PulseType "Time based"
Period "40"
PulseWidth "50"
}
Block {
BlockType Scope
Name "Scope"
Ports [1]
Position [320, 149, 350, 181]
Location [6, 66, 274, 271]
Open on
NumInputPorts "1"
List {
ListType AxesTitles
axes1 "%<SignalLabel>"
}
TimeRange "40"
YMin "-3"
YMax "2"
SaveToWorkspace on
SaveName "Y"
DataFormat "Array"
MaxDataPoints "50000"
}
Block {
BlockType Sum
Name "Sum"
Ports [2, 1]
Position [150, 75, 170, 95]
ShowName off
IconShape "round"
Inputs "|+-"
}
Block {
BlockType Sum
Name "Sum1"
Ports [2, 1]
Position [55, 100, 75, 120]
ShowName off
IconShape "round"
}
Block {
BlockType Sum
Name "Sum2"
Ports [2, 1]
Position [310, 75, 330, 95]
ShowName off
IconShape "round"
}
Block {
BlockType ToWorkspace
Name "To Workspace4"
Position [90, 22, 110, 48]
VariableName "t"
MaxDataPoints "inf"
SampleTime "-1"
SaveFormat "Array"
}
Block {
BlockType TransferFcn
Name "Transfer Fcn2"
Position [345, 66, 410, 104]
Numerator "[K]"
Denominator "[1 3 3 1]"
}
Line {
SrcBlock "Transfer Fcn2"
SrcPort 1
Points [5, 0; 0, 50; -150, 0]
Branch {
Points [0, 30]
DstBlock "Mux"
DstPort 2
}
Branch {
Points [-110, 0]
DstBlock "Sum"
DstPort 2
}
}
Line {
SrcBlock "Pulse\nGenerator"
SrcPort 1
DstBlock "Sum1"
DstPort 1
}
Line {
SrcBlock "Clock"
SrcPort 1
DstBlock "To Workspace4"
DstPort 1
}
Line {
SrcBlock "Mux"
SrcPort 1
DstBlock "Scope"
DstPort 1
}
Line {
SrcBlock "Sum1"
SrcPort 1
DstBlock "Gain"
DstPort 1
}
Line {
SrcBlock "Constant"
SrcPort 1
Points [15, 0]
DstBlock "Sum1"
DstPort 2
}
Line {
SrcBlock "Gain"
SrcPort 1
Points [5, 0]
Branch {
Points [0, 70]
DstBlock "Mux"
DstPort 1
}
Branch {
Points [0, 0]
Branch {
DstBlock "Sum"
DstPort 1
}
Branch {
Points [0, -45]
DstBlock "Gain4"
DstPort 1
}
}
}
Line {
SrcBlock "Sum"
SrcPort 1
Points [0, 0]
Branch {
Points [0, 20; 5, 0]
Branch {
Points [0, 70]
DstBlock "Mux"
DstPort 3
}
Branch {
DstBlock "Derivative"
DstPort 1
}
}
Branch {
Points [55, 0]
DstBlock "Fuzzy Subsystem"
DstPort 1
}
}
Line {
SrcBlock "Derivative"
SrcPort 1
DstBlock "Fuzzy Subsystem"
DstPort 2
}
Line {
SrcBlock "Sum2"
SrcPort 1
DstBlock "Transfer Fcn2"
DstPort 1
}
Line {
SrcBlock "Fuzzy Subsystem"
SrcPort 1
Points [0, 25]
DstBlock "Sum2"
DstPort 2
}
Line {
SrcBlock "Gain4"
SrcPort 1
Points [0, 20]
DstBlock "Sum2"
DstPort 1
}
Annotation {
Name "SIMULINK BLOCK DIAGRAM for FLC design\nChou, Pe"
"nchen, 8/9/2001, 2004/1/6,2005-4-26\nflc3_sampleA.mdl Use with Matlab 7.x on"
"ly."
Position [319, 30]
}
}
}
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