📄 dorsey188b.mdl
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Model {
Name "Dorsey188B"
Version 4.00
SampleTimeColors off
LibraryLinkDisplay "none"
WideLines on
ShowLineDimensions off
ShowPortDataTypes off
RecordCoverage off
CovPath "/"
CovSaveName "covdata"
CovNameIncrementing off
CovHtmlReporting on
BlockNameDataTip off
BlockParametersDataTip off
BlockDescriptionStringDataTip off
ToolBar on
StatusBar on
BrowserShowLibraryLinks off
BrowserLookUnderMasks off
Created "Thu Apr 25 10:49:18 2002"
UpdateHistory "UpdateHistoryNever"
ModifiedByFormat "%<Auto>"
LastModifiedBy "User"
ModifiedDateFormat "%<Auto>"
LastModifiedDate "Thu May 02 06:20:41 2002"
ModelVersionFormat "1.%<AutoIncrement:47>"
ConfigurationManager "none"
SimParamPage "Solver"
StartTime "0.0"
StopTime "1.0"
SolverMode "Auto"
Solver "ode4"
RelTol "1e-3"
AbsTol "auto"
Refine "1"
MaxStep "auto"
MinStep "auto"
MaxNumMinSteps "-1"
InitialStep "auto"
FixedStep "0.01"
MaxOrder 5
OutputOption "RefineOutputTimes"
OutputTimes "[]"
LoadExternalInput off
ExternalInput "[t, u]"
SaveTime on
TimeSaveName "tout"
SaveState off
StateSaveName "xout"
SaveOutput on
OutputSaveName "yout"
LoadInitialState off
InitialState "xInitial"
SaveFinalState off
FinalStateName "xFinal"
SaveFormat "Array"
LimitDataPoints on
MaxDataPoints "1000"
Decimation "1"
AlgebraicLoopMsg "warning"
MinStepSizeMsg "warning"
UnconnectedInputMsg "warning"
UnconnectedOutputMsg "warning"
UnconnectedLineMsg "warning"
InheritedTsInSrcMsg "warning"
SingleTaskRateTransMsg "none"
MultiTaskRateTransMsg "error"
IntegerOverflowMsg "warning"
CheckForMatrixSingularity "none"
UnnecessaryDatatypeConvMsg "none"
Int32ToFloatConvMsg "warning"
SignalLabelMismatchMsg "none"
LinearizationMsg "none"
VectorMatrixConversionMsg "none"
SfunCompatibilityCheckMsg "none"
BlockPriorityViolationMsg "warning"
ArrayBoundsChecking "none"
ConsistencyChecking "none"
ZeroCross on
Profile off
SimulationMode "normal"
RTWSystemTargetFile "grt.tlc"
RTWInlineParameters off
RTWRetainRTWFile off
RTWTemplateMakefile "grt_default_tmf"
RTWMakeCommand "make_rtw"
RTWGenerateCodeOnly off
TLCProfiler off
TLCDebug off
TLCCoverage off
AccelSystemTargetFile "accel.tlc"
AccelTemplateMakefile "accel_default_tmf"
AccelMakeCommand "make_rtw"
ExtModeMexFile "ext_comm"
ExtModeBatchMode off
ExtModeTrigType "manual"
ExtModeTrigMode "normal"
ExtModeTrigPort "1"
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ExtModeTrigDuration 1000
ExtModeTrigHoldOff 0
ExtModeTrigDelay 0
ExtModeTrigDirection "rising"
ExtModeTrigLevel 0
ExtModeArchiveMode "off"
ExtModeAutoIncOneShot off
ExtModeIncDirWhenArm off
ExtModeAddSuffixToVar off
ExtModeWriteAllDataToWs off
ExtModeArmWhenConnect on
ExtModeLogAll on
OptimizeBlockIOStorage on
BufferReuse on
ParameterPooling on
BlockReductionOpt off
BooleanDataType off
BlockDefaults {
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ForegroundColor "black"
BackgroundColor "white"
DropShadow off
NamePlacement "normal"
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
ShowName on
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AnnotationDefaults {
HorizontalAlignment "center"
VerticalAlignment "middle"
ForegroundColor "black"
BackgroundColor "white"
DropShadow off
FontName "Helvetica"
FontSize 10
FontWeight "normal"
FontAngle "normal"
}
LineDefaults {
FontName "Helvetica"
FontSize 9
FontWeight "normal"
FontAngle "normal"
}
System {
Name "Dorsey188B"
Location [289, 82, 747, 279]
Open on
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
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AutoZoom on
ReportName "simulink-default.rpt"
Block {
BlockType Clock
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DisplayTime off
Decimation "10"
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Format "short"
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SampleTime "-1"
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Block {
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Gain "1"
Multiplication "Element-wise(K.*u)"
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Block {
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Multiplication "Element-wise(K.*u)"
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Block {
BlockType Mux
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Position [375, 16, 380, 54]
ShowName off
Inputs "3"
DisplayOption "bar"
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Block {
BlockType SubSystem
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TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
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ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
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PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
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Interpolate on
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Block {
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SaturateOnIntegerOverflow on
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Block {
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Position [90, 75, 120, 105]
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VectorParams1D on
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Value "1"
VectorParams1D on
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Block {
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Value "1"
VectorParams1D on
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Block {
BlockType Derivative
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Position [110, 355, 140, 385]
}
Block {
BlockType SubSystem
Name "Fuzzy Kd Subsystem2"
Ports [3, 1]
Position [265, 165, 345, 205]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
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Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
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PaperType "usletter"
PaperUnits "inches"
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Port "1"
Interpolate on
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Block {
BlockType Inport
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Position [25, 88, 55, 102]
Port "2"
Interpolate on
}
Block {
BlockType Inport
Name "Gain"
Position [30, 53, 60, 67]
Port "3"
Interpolate on
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [115, 75, 165, 115]
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
fis "psch4d"
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Block {
BlockType Product
Name "Product"
Ports [3, 1]
Position [215, 24, 235, 66]
Inputs "3"
Multiplication "Element-wise(.*)"
SaturateOnIntegerOverflow on
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Block {
BlockType Outport
Name "Out1"
Position [270, 38, 300, 52]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
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Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
Points [0, -50]
DstBlock "Product"
DstPort 2
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Line {
SrcBlock "Pass sig"
SrcPort 1
Points [0, 10]
DstBlock "Product"
DstPort 1
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Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Sig in fuzzy"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Product"
DstPort 3
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}
Block {
BlockType SubSystem
Name "Fuzzy Ki Subsystem1"
Ports [3, 1]
Position [250, 98, 335, 142]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "Fuzzy Ki Subsystem1"
Location [373, 82, 705, 245]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "Pass sig"
Position [25, 13, 55, 27]
Port "1"
Interpolate on
}
Block {
BlockType Inport
Name "Sig in fuzzy"
Position [25, 88, 55, 102]
Port "2"
Interpolate on
}
Block {
BlockType Inport
Name "Gain"
Position [30, 53, 60, 67]
Port "3"
Interpolate on
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [115, 75, 165, 115]
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
fis "psch4i"
}
Block {
BlockType Product
Name "Product"
Ports [3, 1]
Position [215, 24, 235, 66]
Inputs "3"
Multiplication "Element-wise(.*)"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Name "Out1"
Position [270, 38, 300, 52]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
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Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Product"
DstPort 3
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Line {
SrcBlock "Sig in fuzzy"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
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Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Pass sig"
SrcPort 1
Points [0, 10]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
Points [0, -50]
DstBlock "Product"
DstPort 2
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Block {
BlockType SubSystem
Name "Fuzzy Kp Subsystem"
Ports [3, 2]
Position [240, 19, 330, 61]
ShowPortLabels on
TreatAsAtomicUnit off
RTWSystemCode "Auto"
RTWFcnNameOpts "Auto"
RTWFileNameOpts "Auto"
System {
Name "Fuzzy Kp Subsystem"
Location [371, 82, 703, 245]
Open off
ModelBrowserVisibility off
ModelBrowserWidth 200
ScreenColor "automatic"
PaperOrientation "landscape"
PaperPositionMode "auto"
PaperType "usletter"
PaperUnits "inches"
ZoomFactor "100"
AutoZoom on
Block {
BlockType Inport
Name "Pass sig"
Position [25, 15, 55, 29]
Port "1"
Interpolate on
}
Block {
BlockType Inport
Name "Sig in fuzzy"
Position [25, 90, 55, 104]
Port "2"
Interpolate on
}
Block {
BlockType Inport
Name "Gain"
Position [30, 55, 60, 69]
Port "3"
Interpolate on
}
Block {
BlockType Reference
Name "Fuzzy Logic \nController"
Ports [1, 1]
Position [115, 75, 165, 115]
FontName "Arial"
SourceBlock "fuzblock/Fuzzy Logic \nController"
SourceType "FIS"
fis "psch4"
}
Block {
BlockType Product
Name "Product"
Ports [3, 1]
Position [215, 24, 235, 66]
Inputs "3"
Multiplication "Element-wise(.*)"
SaturateOnIntegerOverflow on
}
Block {
BlockType Outport
Name "Out1"
Position [270, 40, 300, 54]
Port "1"
OutputWhenDisabled "held"
InitialOutput "[]"
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Block {
BlockType Outport
Name "Out2"
Position [270, 88, 300, 102]
Port "2"
OutputWhenDisabled "held"
InitialOutput "[]"
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Line {
SrcBlock "Fuzzy Logic \nController"
SrcPort 1
Points [0, -50; 20, 0]
Branch {
DstBlock "Product"
DstPort 2
}
Branch {
Points [0, 50]
DstBlock "Out2"
DstPort 1
}
}
Line {
SrcBlock "Pass sig"
SrcPort 1
Points [0, 10]
DstBlock "Product"
DstPort 1
}
Line {
SrcBlock "Product"
SrcPort 1
DstBlock "Out1"
DstPort 1
}
Line {
SrcBlock "Sig in fuzzy"
SrcPort 1
DstBlock "Fuzzy Logic \nController"
DstPort 1
}
Line {
SrcBlock "Gain"
SrcPort 1
DstBlock "Product"
DstPort 3
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}
Block {
BlockType Gain
Name "Gain"
Position [140, 73, 175, 107]
Gain "Ki"
Multiplication "Element-wise(K.*u)"
SaturateOnIntegerOverflow on
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Block {
BlockType Gain
Name "Gain1"
Position [140, 118, 175, 152]
Gain "Kp"
Multiplication "Element-wise(K.*u)"
SaturateOnIntegerOverflow on
}
Block {
BlockType Gain
Name "Gain10"
Position [335, 353, 390, 387]
Gain "1-SW"
Multiplication "Element-wise(K.*u)"
SaturateOnIntegerOverflow on
}
Block {
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