interruptconfig.c

freescale 协处理器应用相关实例

/******************************************************************************
													Copyright (c) Freescale 2006
File Name    : $RCSfile: InterruptConfig.c,v $

Engineer     : $Author: r32151 $

Location     : EKB

Date Created : 11/5/2005

Current Revision :	$Revision: 1.1 $

Notes        : Routines for configuring the S12X interrupt system including 
               the XGate interrupt co processor (which requires copying of 
               it's code to RAM).
               The priority of each interrupt source and whether it is to be
               serviced by the Core CPU or the XGate is assigned in a simple 
               table which should be modified as required. 
             
             **************************************************************** 
             * SIZE OF THE TWO XGATE STACKS MUST BE DEFINED IN INTERRPUTS.H *
.				 ****************************************************************



               
UPDATE HISTORY                                                            
REV  AUTHOR    DATE        DESCRIPTION OF CHANGE                          
---  ------    --------    ---------------------                          
1.0  r32151    01/03/05    - initial coding
1.1  r32151    26/01/06    - Changed initialisation of the XGATE stacks
                             to use two arrays XgateHiStack[] and 
                             XgateLoStack[]. This allows the XGATE RAM
                             memory map to be modified without changing the 
                             source code addresses.
                             Size of the arrays need to be defined in 
                             interrupts.h.
                             Updated ConfigureInterrupts to reference the
                             arrays when initialising the XGATE registers.             
 
     *******************************************************************
     * File created by: Freescale East Kilbride MCD Applications Group *
     *******************************************************************

                                                                          
******************************************************************************/
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/************************* Include Files *************************************/
#include "s12x_peripherals.h"
#include "target.h"
#include "InterruptConfig.h"
#include "Xgate_vectors.h"
#include "s12x_vectors.h"
#include "interrupts.h"

/************************* typedefs ******************************************/
/* in InterruptConfig.h */

/************************* #defines ******************************************/
/* in InterruptConfig.h */

#ifdef XG_FREEZES
#define _XGFRZ XGFRZ
#else
#define _XGFRZ 0
#endif

#ifdef XG_FAKE_ACTIVITY
#define _XGFACT XGFACT
#else
#define _XGFACT 0
#endif

/************************* Constants *****************************************/
#pragma CONST_SEG DEFAULT

/************************* Global Variables **********************************/
#pragma DATA_SEG XGATE_STACKS
/* these two arrays are used to define space in the XGATE RAM for the low and
   high priority stacks. They not are referenced in the application as they 
   are only used implicitly for XGATE stack operations. */
volatile unsigned int XgateHiStack[XGATE_HI_STACK_SIZE];
volatile unsigned int XgateLoStack[XGATE_LO_STACK_SIZE];

#pragma DATA_SEG DEFAULT

/************************* function prototypes *******************************/
/* in InterruptConfig.h */

/************************* Functions *****************************************/
#pragma CODE_SEG DEFAULT

/*****************************************************************************
InterruptConfigurationTable.
Interrupt configuration table for S12XDP512. 
This is the configuration table for interrupt requests used to set the priority
and whether it is handled by the CPU or XGATE
The data in this table must be copied to the banks of INT_CFDATA0..7 registers.

			 *******************************************************
          *   Priority Level can be from PRIOLVL1 to PRIOLVL7   *
			 *******************************************************
          * To route servicing to Xgate change to PRIOLVLx|RQST *
          *******************************************************
             
*****************************************************************************/
const unsigned char InterruptConfigurationTable[] = 
{                                      
    _INT_PRI_3C | _INT_SER_3C,                 /* 0x3C ATD1 compare                       (XG Channel 1E) */                           
    _INT_PRI_3E | _INT_SER_40,                 /* 0x3E ATD0 compare                       (XG Channel 1F) */                           
    _INT_PRI_40 | _INT_SER_42,                 /* 0x40 TIM Pulse accumulator input edge   (XG Channel 20) */    
    _INT_PRI_42 | _INT_SER_42,                 /* 0x42 TIM Pulse accumulator A overflow   (XG Channel 21) */    
    _INT_PRI_44 | _INT_SER_44,                 /* 0x44 TIM overflow                       (XG Channel 22) */
    _INT_PRI_46 | _INT_SER_46,                 /* 0x46 TIM channel 7                      (XG Channel 23) */                                
    _INT_PRI_48 | _INT_SER_48,                 /* 0x48 TIM channel 6                      (XG Channel 24) */
    _INT_PRI_4A | _INT_SER_4A,                 /* 0x4A TIM channel 5                      (XG Channel 25) */
    _INT_PRI_4C | _INT_SER_4C,                 /* 0x4C TIM channel 4                      (XG Channel 26) */
    _INT_PRI_4E | _INT_SER_4E,                 /* 0x4E TIM channel 3                      (XG Channel 27) */
    _INT_PRI_50 | _INT_SER_50,                 /* 0x50 TIM channel 2                      (XG Channel 28) */
    _INT_PRI_52 | _INT_SER_52,                 /* 0x52 TIM channel 1                      (XG Channel 29) */
    _INT_PRI_54 | _INT_SER_54,                 /* 0x54 TIM channel 0                      (XG Channel 2A) */
    _INT_PRI_56 | _INT_SER_56,                 /* 0x56 SCI7                               (XG Channel 2B) */           
    _INT_PRI_58 | _INT_SER_58,                 /* 0x58 Periodic Interrupt Timer 7         (XG Channel 2C) */         
    _INT_PRI_5A | _INT_SER_5A,                 /* 0x5A Periodic Interrupt Timer 6         (XG Channel 2D) */         
    _INT_PRI_5C | _INT_SER_5C,                 /* 0x5C Periodic Interrupt Timer 5         (XG Channel 2E) */         
    _INT_PRI_5E | _INT_SER_5E,                 /* 0x5E Periodic Interrupt Timer 4         (XG Channel 2F) */         
    _INT_PRI_60 | _INT_SER_60,                 /* 0x60 Reserved                           (XG Channel 30) */
    _INT_PRI_62 | _INT_SER_62,                 /* 0x62 Reserved                           (XG Channel 31) */
    _INT_PRI_64 | _INT_SER_64,                 /* 0x64 XGATE Software Trigger 7           (XG Channel 32) */
    _INT_PRI_66 | _INT_SER_66,                 /* 0x66 XGATE Software Trigger 6           (XG Channel 33) */
    _INT_PRI_68 | _INT_SER_68,                 /* 0x68 XGATE Software Trigger 5           (XG Channel 34) */
    _INT_PRI_6A | _INT_SER_6A,                 /* 0x6A XGATE Software Trigger 4           (XG Channel 35) */
    _INT_PRI_6C | _INT_SER_6C,                 /* 0x6C XGATE Software Trigger 3           (XG Channel 36) */
    _INT_PRI_6E | _INT_SER_6E,                 /* 0x6E XGATE Software Trigger 2           (XG Channel 37) */
    _INT_PRI_70 | _INT_SER_70,                 /* 0x70 XGATE Software Trigger 1           (XG Channel 38) */
    _INT_PRI_72 | _INT_SER_72,                 /* 0x72 XGATE Software Trigger 0           (XG Channel 39) */
    _INT_PRI_74 | _INT_SER_74,                 /* 0x74 Periodic Interrupt Timer 3         (XG Channel 3A) */
    _INT_PRI_76 | _INT_SER_76,                 /* 0x76 Periodic Interrupt Timer 2         (XG Channel 3B) */
    _INT_PRI_78 | _INT_SER_78,                 /* 0x78 Periodic Interrupt Timer 1         (XG Channel 3C) */
    _INT_PRI_7A | _INT_SER_7A,                 /* 0x7A Periodic Interrupt Timer 0         (XG Channel 3D) */
    _INT_PRI_7C | _INT_SER_7C,                 /* 0x7C Reserved                           (XG Channel 3E) */
    _INT_PRI_7E | _INT_SER_7E,                 /* 0x7E API Autonomous Periodical Interrupt(XG Channel 3F) */
    _INT_PRI_80 | _INT_SER_80,                 /* 0x80 LVI Low Voltage Interrupt          (XG Channel 40) */
    _INT_PRI_82 | _INT_SER_82,                 /* 0x82 IIC1                               (XG Channel 41) */
    _INT_PRI_84 | _INT_SER_84,                 /* 0x84 SCI5                               (XG Channel 42) */
    _INT_PRI_86 | _INT_SER_86,                 /* 0x86 SCI4                               (XG Channel 43) */
    _INT_PRI_88 | _INT_SER_88,                 /* 0x88 SCI3                               (XG Channel 44) */
    _INT_PRI_8A | _INT_SER_8A,                 /* 0x8A SCI2                               (XG Channel 45) */
    _INT_PRI_8C | _INT_SER_8C,                 /* 0x8C PWM Emergency Shutdown             (XG Channel 46) */
    _INT_PRI_8E | _INT_SER_8E,                 /* 0x8E Port P Interrupt                   (XG Channel 47) */
    _INT_PRI_90 | _INT_SER_90,                 /* 0x90 MSCAN 4 transmit                   (XG Channel 48) */
    _INT_PRI_92 | _INT_SER_92,                 /* 0x92 MSCAN 4 receive                    (XG Channel 49) */
    _INT_PRI_94 | _INT_SER_94,                 /* 0x94 MSCAN 4 errors                     (XG Channel 4A) */