per_xex100_m22e.lst

freescale 协处理器应用相关实例

ANSI-C/cC++ Compiler for HC12 V-5.0.30 Build 6157, Jun  7 2006

    1:  /******************************************************************************
    2:                                                     COPYRIGHT (c) FREESCALE 2005   
    3:  FILE NAME: per_XEx100_M22E.c     REVISION 1.0                                        
    4:                                                                            
    5:  PURPOSE: Declaration of peripheral variables for an MC9S12XEP100
    6:           Mask Set: M22E                    
    7:                                                                                                                                                       
    8:  DESCRIPTION:  declarations of control register blocks for on-chip peripherals.        
    9:                                                                             
   10:  UPDATE HISTORY                                                            
   11:  REV      AUTHOR      DATE         DESCRIPTION OF CHANGE                    
   12:  ---      ------      ---------    ---------------------                   
   13:  1.0      r32151      13/10/05     Initial coding 
   14:  1.1      r32151      26/01/06     xxx0AD0 PIM ports added
   15:  
   16:  
   17:        *****************************************************************
   18:        *File created by: Freescale East Kilbride MCD Applications Group*
   19:        *****************************************************************
   20:  
   21:                                                                            
   22:  ******************************************************************************/
   23:  /******************************************************************************
   24:  * Peripheral   Peripheral UG    Version   Doc. Order #      Header File
   25:  * ----------   ---------------  -------   ---------------   ---------------
   26:  * ATD          ATD_12B16C       V01       S12XATD12B16CV1/D S12XATD12B16CV1.H
   27:  * CRG          S12XE_CRG        V01       S12XECRGV1/D      S12XECRGV1.H
   28:  * DEBUG        S12X_DBG         V03       S12XDBGV3/D       S12XDBGV3.H
   29:  * EBI          S12X_EBI         V02       S12XEBIV3/D       S12XEBIV3.H
   30:  * IIC          IIC              V03       S12IICV3/D        S12IICV3.H
   31:  * INTERRUPT    S12X_INTERRUPT   V02       S12XINTV2/D       S12XINTV2.H
   32:  * MMC          S12X_MMC         V04       S12XMMCV4/D       S12MMCIV4.H
   33:  * MSCAN        MSCAN            V03       S12MSCANV3/D      S12MSCANV3.H
   34:  * PWM          PWM_8B8C         V01       S12PWM8B8CV1/D    S12PWM8B8CV1.H
   35:  * SCI          SCI              V05       S12SCIV5/D        S12SCIV5.H
   36:  * SPI          SPI              V04       S12SPIV5/D        S12SPIV5.H
   37:  * VREG         VREG             V01       S12VREGL_3V3V1/D  S12VREGL_3V3V1.H
   38:  * PIT          PIT_24B8C        V01       S12PIT24B8CV1/D   S12PIT24B8CV1.H
   39:  * XGATE        XGATE            V03       S12XGATEV3/D      S12XGATEV3.H	  
   40:  * ECT          ECT_16B8C        V03       S12ECT16B8CV3/D   S12ECT16B8CV3.H
   41:  * TIMER        TIM16B8C         V02       S12TIM16B8CV2/D   S12TIM16B8CV2.H
   42:  * PIM          PIM_9XEP512      V01       S12XEP512PIMV1/D  S12XEP512PIMV1.H
   43:  
   44:  * EEPROM       EETSX4K          V02       S12XEETX4KV2/D    S12XEETX4KV2.H
   45:  * FLASH        FTSX512K4        V02       S12XFTX512K4V2/D  S12XFTX512K4V2.H
   46:  ******************************************************************************/
   47:  /*===========================================================================*/
   48:  /* Freescale reserves the right to make changes without further notice to any*/
   49:  /* product herein to improve reliability, function, or design. Freescale does*/
   50:  /* not assume any  liability arising  out  of the  application or use of any */
   51:  /* product,  circuit, or software described herein;  neither  does it convey */
   52:  /* any license under its patent rights  nor the  rights of others.  Freescale*/
   53:  /* products are not designed, intended,  or authorized for use as components */
   54:  /* in  systems  intended  for  surgical  implant  into  the  body, or  other */
   55:  /* applications intended to support life, or  for any  other application  in */
   56:  /* which the failure of the Freescale product  could create a situation where*/
   57:  /* personal injury or death may occur. Should Buyer purchase or use Freescale*/
   58:  /* products for any such intended  or unauthorized  application, Buyer shall */
   59:  /* indemnify and  hold  Freescale  and its officers, employees, subsidiaries,*/
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   61:  /* and expenses, and reasonable  attorney  fees arising  out of, directly or */
   62:  /* indirectly,  any claim of personal injury  or death  associated with such */
   63:  /* unintended or unauthorized use, even if such claim alleges that  Freescale*/
   64:  /* was negligent regarding the  design  or manufacture of the part. Freescale*/
   65:  /* and the Freescale logo* are registered trademarks of Freescale Ltd.       */
   66:  /*****************************************************************************/
   67:  
   68:  #include "per_XEx100_M22E.h"
   69:  
   70:  volatile tPORT    PORTA    @0x0000;    /* Port A Data Register */
   71:  volatile tPORT    PORTB    @0x0001;    /* Port B Data Register */
   72:  volatile tPORT    DDRA     @0x0002;    /* Port A Data Direction Register */
   73:  volatile tPORT    DDRB     @0x0003;    /* Port B Data Direction Register */
   74:  volatile tPORT    PORTC    @0x0004;    /* Port C Data Register */
   75:  volatile tPORT    PORTD    @0x0005;    /* Port D Data Register */
   76:  volatile tPORT    DDRC     @0x0006;    /* Port C Data Direction Register */
   77:  volatile tPORT    DDRD     @0x0007;    /* Port D Data Direction Register */
   78:  volatile tPORT    PORTE    @0x0008;    /* Port E Data Register */
   79:  volatile tPORT    DDRE     @0x0009;    /* Port E Data Direction Register */
   80:  
   81:  volatile tMMCCTL0 MMCCTL0  @0x000A;    /* MMC Control Register 0 - rev 2  */
   82:  volatile tMODE    MODE     @0x000B;    /* Mode Register => */
   83:  volatile tPUCR    PUCR     @0x000C;    /* Pull-up Control Register */
   84:  volatile tRDRIV   RDRIV    @0x000D;    /* Reduced Drive Register */
   85:  volatile tEBICTL0 EBICTL0  @0x000E;    /* EBI Control Register 0 */
   86:  volatile tEBICTL1 EBICTL1  @0x000F;    /* EBI Control Register 1 */
   87:  volatile tGPAGE   GPAGE    @0x0010;    /* Global Page Index Register */
   88:  volatile tDIRECT  DIRECT   @0x0011;    /* Direct Page Register */
   89:  volatile tMMCCTL1 MMCCTL1  @0x0013;    /* MMC Control Register 1 */
   90:  volatile tPPAGE   PPAGE    @0x0015;    /* Program Page Index Register */
   91:  volatile tRPAGE   RPAGE    @0x0016;    /* RAM Page Index Register */
   92:  volatile tEPAGE   EPAGE    @0x0017;    /* EEPROM Page Index Register */
   93:  volatile tREG16   PARTID   @0x001A;    /* Part ID */
   94:  volatile tECLKCTL ECLKCTL  @0x001C;    /* E-clock Control Register */
   95:  volatile tIRQCR   IRQCR    @0x001E;    /* IRQ Control Register */
   96:  volatile tDBG     DBG      @0x0020;    /* DBG module */
   97:  
   98:  volatile tPORT    PORTK    @0x0032;    /* Port K Data Register */
   99:  volatile tPORT    DDRK     @0x0033;    /* Port K Data Direction Register */
  100:  
  101:  volatile tCRG     CRG      @0x0034;    /* Clock and Reset Generator Module */
  102:  
  103:  volatile tECT     ECT      @0x0040;    /* Enhanced Capture Timer Module */
  104:  
  105:  volatile tATD16   ATD1     @0x0080;    /* ATD Module 0 - 16 Channel ATD */
  106:  volatile tIIC     IIC1     @0x00B0;    /* IIC Module 1 */
  107:  volatile tSCI     SCI2     @0x00B8;    /* SCI Module 2 */
  108:  volatile tSCI     SCI3     @0x00C0;    /* SCI Module 3 */
  109:  volatile tSCI     SCI0     @0x00C8;    /* SCI Module 0 */
  110:  volatile tSCI     SCI1     @0x00D0;    /* SCI Module 1 */
  111:  volatile tSPI     SPI0     @0x00D8;    /* SPI Module 0 */
  112:  volatile tIIC     IIC0     @0x00E0;    /* IIC Module 0 */
  113:  volatile tSPI     SPI1     @0x00F0;    /* SPI Module 1 */
  114:  volatile tSPI     SPI2     @0x00F8;    /* SPI Module 2 */
  115:  
  116:  volatile tFTM     FTM      @0x0100;    /* NVM Control Registers */
  117:  
  118:  volatile tMPU     MPU      @0x0114;    /* MPU Protection Control*/
  119: