interruptconfig.lst

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    1:  /******************************************************************************
    2:  													Copyright (c) Freescale 2006
    3:  File Name    : $RCSfile: InterruptConfig.c,v $
    4:  
    5:  Engineer     : $Author: r32151 $
    6:  
    7:  Location     : EKB
    8:  
    9:  Date Created : 11/5/2005
   10:  
   11:  Current Revision :	$Revision: 1.1 $
   12:  
   13:  Notes        : Routines for configuring the S12X interrupt system including 
   14:                 the XGate interrupt co processor (which requires copying of 
   15:                 it's code to RAM).
   16:                 The priority of each interrupt source and whether it is to be
   17:                 serviced by the Core CPU or the XGate is assigned in a simple 
   18:                 table which should be modified as required. 
   19:               
   20:               **************************************************************** 
   21:               * SIZE OF THE TWO XGATE STACKS MUST BE DEFINED IN INTERRPUTS.H *
   22:  .				 ****************************************************************
   23:  
   24:  
   25:  
   26:                 
   27:  UPDATE HISTORY                                                            
   28:  REV  AUTHOR    DATE        DESCRIPTION OF CHANGE                          
   29:  ---  ------    --------    ---------------------                          
   30:  1.0  r32151    01/03/05    - initial coding
   31:  1.1  r32151    26/01/06    - Changed initialisation of the XGATE stacks
   32:                               to use two arrays XgateHiStack[] and 
   33:                               XgateLoStack[]. This allows the XGATE RAM
   34:                               memory map to be modified without changing the 
   35:                               source code addresses.
   36:                               Size of the arrays need to be defined in 
   37:                               interrupts.h.
   38:                               Updated ConfigureInterrupts to reference the
   39:                               arrays when initialising the XGATE registers.             
   40:   
   41:       *******************************************************************
   42:       * File created by: Freescale East Kilbride MCD Applications Group *
   43:       *******************************************************************
   44:  
   45:                                                                            
   46:  ******************************************************************************/
   47:  /*===========================================================================*/
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   66:  /*****************************************************************************/
   67:  
   68:  /************************* Include Files *************************************/
   69:  #include "s12x_peripherals.h"
   70:  #include "target.h"
   71:  #include "InterruptConfig.h"
   72:  #include "Xgate_vectors.h"
   73:  #include "s12x_vectors.h"
   74:  #include "interrupts.h"
   75:  
   76:  /************************* typedefs ******************************************/
   77:  /* in InterruptConfig.h */
   78:  
   79:  /************************* #defines ******************************************/
   80:  /* in InterruptConfig.h */
   81:  
   82:  #ifdef XG_FREEZES
   83:  #define _XGFRZ XGFRZ
   84:  #else
   85:  #define _XGFRZ 0
   86:  #endif
   87:  
   88:  #ifdef XG_FAKE_ACTIVITY
   89:  #define _XGFACT XGFACT
   90:  #else
   91:  #define _XGFACT 0
   92:  #endif
   93:  
   94:  /************************* Constants *****************************************/
   95:  #pragma CONST_SEG DEFAULT
   96:  
   97:  /************************* Global Variables **********************************/
   98:  #pragma DATA_SEG XGATE_STACKS
   99:  /* these two arrays are used to define space in the XGATE RAM for the low and
  100:     high priority stacks. They not are referenced in the application as they 
  101:     are only used implicitly for XGATE stack operations. */
  102:  volatile unsigned int XgateHiStack[XGATE_HI_STACK_SIZE];
  103:  volatile unsigned int XgateLoStack[XGATE_LO_STACK_SIZE];
  104:  
  105:  #pragma DATA_SEG DEFAULT
  106:  
  107:  /************************* function prototypes *******************************/
  108:  /* in InterruptConfig.h */
  109:  
  110:  /************************* Functions *****************************************/
  111:  #pragma CODE_SEG DEFAULT
  112:  
  113:  /*****************************************************************************
  114:  InterruptConfigurationTable.
  115:  Interrupt configuration table for S12XDP512. 
  116:  This is the configuration table for interrupt requests used to set the priority
  117:  and whether it is handled by the CPU or XGATE
  118:  The data in this table must be copied to the banks of INT_CFDATA0..7 registers.
  119:  
  120:  			 *******************************************************
  121:            *   Priority Level can be from PRIOLVL1 to PRIOLVL7   *
  122:  			 *******************************************************
  123:            * To route servicing to Xgate change to PRIOLVLx|RQST *
  124:            *******************************************************
  125:               
  126:  *****************************************************************************/
  127:  const unsigned char InterruptConfigurationTable[] = 
  128:  {                                      
  129:      _INT_PRI_3C | _INT_SER_3C,                 /* 0x3C ATD1 compare                       (XG Channel 1E) */                           
  130:      _INT_PRI_3E | _INT_SER_40,                 /* 0x3E ATD0 compare                       (XG Channel 1F) */                           
  131:      _INT_PRI_40 | _INT_SER_42,                 /* 0x40 TIM Pulse accumulator input edge   (XG Channel 20) */    
  132:      _INT_PRI_42 | _INT_SER_42,                 /* 0x42 TIM Pulse accumulator A overflow   (XG Channel 21) */    
  133:      _INT_PRI_44 | _INT_SER_44,                 /* 0x44 TIM overflow                       (XG Channel 22) */
  134:      _INT_PRI_46 | _INT_SER_46,                 /* 0x46 TIM channel 7                      (XG Channel 23) */                                
  135:      _INT_PRI_48 | _INT_SER_48,                 /* 0x48 TIM channel 6                      (XG Channel 24) */
  136:      _INT_PRI_4A | _INT_SER_4A,                 /* 0x4A TIM channel 5                      (XG Channel 25) */
  137:      _INT_PRI_4C | _INT_SER_4C,                 /* 0x4C TIM channel 4                      (XG Channel 26) */
  138:      _INT_PRI_4E | _INT_SER_4E,                 /* 0x4E TIM channel 3                      (XG Channel 27) */
  139:      _INT_PRI_50 | _INT_SER_50,                 /* 0x50 TIM channel 2                      (XG Channel 28) */
  140:      _INT_PRI_52 | _INT_SER_52,                 /* 0x52 TIM channel 1                      (XG Channel 29) */
  141:      _INT_PRI_54 | _INT_SER_54,                 /* 0x54 TIM channel 0                      (XG Channel 2A) */
  142:      _INT_PRI_56 | _INT_SER_56,                 /* 0x56 SCI7                               (XG Channel 2B) */           
  143:      _INT_PRI_58 | _INT_SER_58,                 /* 0x58 Periodic Interrupt Timer 7         (XG Channel 2C) */         
  144:      _INT_PRI_5A | _INT_SER_5A,                 /* 0x5A Periodic Interrupt Timer 6         (XG Channel 2D) */         
  145:      _INT_PRI_5C | _INT_SER_5C,                 /* 0x5C Periodic Interrupt Timer 5         (XG Channel 2E) */         
  146:      _INT_PRI_5E | _INT_SER_5E,                 /* 0x5E Periodic Interrupt Timer 4         (XG Channel 2F) */         
  147:      _INT_PRI_60 | _INT_SER_60,                 /* 0x60 Reserved                           (XG Channel 30) */
  148:      _INT_PRI_62 | _INT_SER_62,                 /* 0x62 Reserved                           (XG Channel 31) */
  149:      _INT_PRI_64 | _INT_SER_64,                 /* 0x64 XGATE Software Trigger 7           (XG Channel 32) */
  150:      _INT_PRI_66 | _INT_SER_66,                 /* 0x66 XGATE Software Trigger 6           (XG Channel 33) */