📄 s12x_e_io.lst
字号:
214: /* Configure Pull-polarity */
215: PPSJ.byte = ALL_PULLED_DOWN;
0088 7b0000 [3] STAB PPSJ
216: /* Enable Pull devices */
217: PERJ.byte = ALL_PULLS_ON;
008b 7b0000 [3] STAB PERJ
218: /* drive level */
219: RDRJ.byte = ALL_REDUCED_DRIVE;
008e 7b0000 [3] STAB RDRJ
220: /* port data */
221: PTJ.byte = ALL_LOW;
0091 790000 [3] CLR PTJ
222: /* port direction */
223: DDRJ.byte = ALL_INPUTS;
0094 790000 [3] CLR DDRJ
224: /* Clear all interrupt flags */
225: PIFJ.byte = 0xFF;
0097 7b0000 [3] STAB PIFJ
226: /* Enable interrupts */
227: PIEJ.byte = 0x00;
009a 790000 [3] CLR PIEJ
228:
229: /* PORT R */
230: /* Configure Pull-polarity */
231: PPSR.byte = ALL_PULLED_DOWN;
009d 7b0000 [3] STAB PPSR
232: /* Enable Pull devices */
233: PERR.byte = ALL_PULLS_ON;
00a0 7b0000 [3] STAB PERR
234: /* drive level */
235: RDRR.byte = ALL_REDUCED_DRIVE;
00a3 7b0000 [3] STAB RDRR
236: /* port data */
237: PTR.byte = ALL_LOW;
00a6 790000 [3] CLR PTR
238: /* port direction */
239: DDRR.byte = ALL_INPUTS;
00a9 790000 [3] CLR DDRR
240:
241: /* PORT L */
242: /* Configure Pull-polarity */
243: PPSL.byte = ALL_PULLED_DOWN;
00ac 7b0000 [3] STAB PPSL
244: /* Enable Pull devices */
245: PERL.byte = ALL_PULLS_ON;
00af 7b0000 [3] STAB PERL
246: /* drive level */
247: RDRL.byte = ALL_REDUCED_DRIVE;
00b2 7b0000 [3] STAB RDRL
248: /* Configure wired-or outputs */
249: WOML.byte = 0x00;
00b5 790000 [3] CLR WOML
250: /* port data */
251: PTL.byte = ALL_LOW;
00b8 790000 [3] CLR PTL
252: /* port direction */
253: DDRL.byte = ALL_INPUTS;
00bb 790000 [3] CLR DDRL
254:
255: /* PORT F */
256: /* Configure Pull-polarity */
257: PPSF.byte = ALL_PULLED_DOWN;
00be 7b0000 [3] STAB PPSF
258: /* Enable Pull devices */
259: PERF.byte = ALL_PULLS_ON;
00c1 7b0000 [3] STAB PERF
260: /* drive level */
261: RDRF.byte = ALL_REDUCED_DRIVE;
00c4 7b0000 [3] STAB RDRF
262: /* port data */
263: PTF.byte = ALL_LOW;
00c7 790000 [3] CLR PTF
264: /* port direction */
265: DDRF.byte = ALL_INPUTS;
00ca 790000 [3] CLR DDRF
266:
267:
268: /******* ATD PORTS ********/
269: /* In order to use the digital input function the ATDIEN bit needs to be set */
270: /* ! NOTE: ATD port pull-ups are active for both digital and analog inputs ! */
271: /*!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!*/
272:
273: /*for PAD[7:0] */
274: PER1AD0.byte = ALL_PULLS_OFF; /* Port AD0 Pull-up Enable */
00cd 790000 [3] CLR PER1AD0
275: ATD0.atddien1.byte = 0x00; /* 1 = digital input enabled */
00d0 790000 [3] CLR ATD0:13
276: RDR1AD0.byte = ALL_REDUCED_DRIVE; /* Port AD0 Reduced Drive Register 1 */
00d3 7b0000 [3] STAB RDR1AD0
277: PT1AD0.byte = ALL_LOW; /* Port AD0 I/O Register 1 */
00d6 790000 [3] CLR PT1AD0
278: DDR1AD0.byte = ALL_INPUTS; /* Port AD0 Data Direction Register 1 */
00d9 790000 [3] CLR DDR1AD0
279:
280: /*for PAD[15:8] */
281: PER0AD0.byte = ALL_PULLS_OFF; /* Port AD1 Pull-up Enable */
00dc 790000 [3] CLR PER0AD0
282: ATD0.atddien0.byte = 0x00; /* 1 = digital input enabled */
00df 790000 [3] CLR ATD0:12
283: RDR0AD0.byte = ALL_REDUCED_DRIVE; /* Port AD1 Reduced Drive Register 1 */
00e2 7b0000 [3] STAB RDR0AD0
284: PT0AD0.byte = ALL_LOW; /* Port AD1-1 I/O Register 1 */
00e5 790000 [3] CLR PT0AD0
285: DDR0AD0.byte = ALL_INPUTS; /* Port AD1 Data Direction Register 0 */
00e8 790000 [3] CLR DDR0AD0
286:
287: /*for PAD[23:16] */
288: PER1AD1.byte = ALL_PULLS_OFF; /* Port AD1 Pull-up Enable */
00eb 790000 [3] CLR PER1AD1
289: ATD1.atddien1.byte = 0x00; /* 1 = digital input enabled */
00ee 790000 [3] CLR ATD1:13
290: RDR1AD1.byte = ALL_REDUCED_DRIVE; /* Port AD1 Reduced Drive Register 1 */
00f1 7b0000 [3] STAB RDR1AD1
291: PT1AD1.byte = ALL_LOW; /* Port AD1-1 I/O Register 1 */
00f4 790000 [3] CLR PT1AD1
292: DDR1AD1.byte = ALL_INPUTS; /* Port AD1 Data Direction Register 0 */
00f7 790000 [3] CLR DDR1AD1
293:
294: /*for PAD[31:24] */
295: PER0AD1.byte = ALL_PULLS_OFF; /* Port AD1 Pull-up Enable */
00fa 790000 [3] CLR PER0AD1
296: ATD1.atddien0.byte = 0x00; /* 1 = digital input enabled */
00fd 790000 [3] CLR ATD1:12
297: RDR0AD1.byte = ALL_REDUCED_DRIVE; /* Port AD1 Reduced Drive Register 0 */
0100 7b0000 [3] STAB RDR0AD1
298: PT0AD1.byte = ALL_LOW; /* Port AD1-0 I/O Register 0 */
0103 790000 [3] CLR PT0AD1
299: DDR0AD1.byte = ALL_INPUTS; /* Port AD1 Data Direction Register 0 */
0106 790000 [3] CLR DDR0AD1
300:
301:
302: /***** module routing *****/
303:
304: /* Module Routing Register */
305: MODRR.byte = 0;
0109 790000 [3] CLR MODRR
306: /* XE-family -----------------
307: Rx Tx
308: modrr[0:1] CAN0 routing 0:0 => PM0:PM1
309: 0:1 => PM2:PM3
310: 1:0 => PM4:PM5
311: 1:1 => PJ6:PJ7
312:
313: Rx Tx
314: modrr[3:2] CAN4 routing 0:0 => PJ6:PJ7
315: 0:1 => PM4:PM5
316: 1:0 => PM6:PM7
317: 1:1 => reserved
318:
319: MISO:MOSI:SCK :SS
320: modrr[4] SPI0 routing 0 => PS4: PS5: PS6 :PS7
321: 1 => PM2: PM4: PM5 :PM3
322:
323: MISO:MOSI:SCK :SS
324: modrr[5] SPI1 routing 0 => PP0: PP1: PP2 :PP3
325: 1 => PH0: PH1: PH2 :PH3
326:
327: MISO:MOSI:SCK :SS
328: modrr[6] SPI2 routing 0 => PP4: PP5: PP7 :PP6
329: 1 => PH4: PH5: PH6 :PH7
330:
331: modrr[7] reserved */
332:
333:
334: /* PORT L Module Routing Register */
335: PTLRR.byte = 0;
010c 790000 [3] CLR PTLRR
336: /* XE-family -----------------
337: Tx :Rx
338: ptlrr[4] SCI4 routing 0 => PH5:PH4
339: 1 => PL1:PL0
340:
341: Tx :Rx
342: ptlrr[5] SCI5 routing 0 => PH7:PH6
343: 1 => PL3:PL2
344:
345: Tx :Rx
346: ptlrr[6] SCI6 routing 0 => PH1:PH0
347: 1 => PL5:PL4
348:
349: Tx :Rx
350: ptlrr[7] SCI7 routing 0 => PH3:PH2
351: 1 => PL7:PL6
352:
353: ptlrr[0:3] reserved */
354:
355: /* PORT F Module Routing Register */
356: PTFRR.byte = 0;
010f 790000 [3] CLR PTFRR
357: /* XE-family -----------------
358:
359: ptfrr[0] CS0 routing 0 => PJ4
360: 1 => PF0
361:
362: ptfrr[1] CS1 routing 0 => PJ2
363: 1 => PF1
364:
365: ptfrr[2] CS2 routing 0 => PJ5
366: 1 => PF2
367:
368: ptfrr[3] CS3 routing 0 => PJ0
369: 1 => PF3
370:
371: SCL:SDA
372: ptfrr[4] IIC0 routing 0 => PJ7:PJ6
373: 1 => PF5:PF4
374:
375: Tx :Rx
376: ptfrr[5] SCI3 routing 0 => PM7:PM6
377: 1 => PF7:PF6
378:
379:
380: ptfrr[7:6] reserved */
381:
382:
383: /* PORT R Module Routing Register */
384: PTRRR.byte = 0;
0112 790000 [3] CLR PTRRR
385: /* XE-family -----------------
386:
387: ptrrr[0] TIM CH0 routing 0 => PR0
388: 1 => PP0
389:
390: ptrrr[1] TIM CH1 routing 0 => PR1
391: 1 => PP1
392:
393: ptrrr[2] TIM CH2 routing 0 => PR2
394: 1 => PP2
395:
396: ptrrr[3] TIM CH3 routing 0 => PR3
397: 1 => PP3
398:
399: ptrrr[4] TIM CH4 routing 0 => PR4
400: 1 => PP4
401:
402: ptrrr[5] TIM CH5 routing 0 => PR5
403: 1 => PP5
404:
405: ptrrr[6] TIM CH6 routing 0 => PR6
406: 1 => PP6
407:
408: ptrrr[7] TIM CH7 routing 0 => PR7
409: 1 => PP7 */
410:
411:
412:
413: /***** ECKL options *****/
414:
415: /* ECLK available on PortE.4, ECLKx2 available on Port E.7
416: - note, keeping port E configured for reduced drive
417: will minimise ECLK generated noise */
418: #ifdef ECLK_OUT
419: // ECLKDIV = 1 to 32; DEFINED IN TARGET.H
420: /* select one: */
421: ECLKCTL.byte = NCLKX2|NECLK; /* ECLKx2 off. ECLK off */
422: // ECLKCTL.byte = NECLK ; /* ECLKx2 on. ECLK off */
423: // ECLKCTL.byte = NCLKX2|(ECLKDIV-1); /* ECLKx2 off. ECLK/ECLKDIV on */
424: // ECLKCTL.byte = NCLKX2|(ECLKDIV-1)|DIV16; /* ECLKx2 off. ECLK/(ECLKDIV*16) on */
425: // ECLKCTL.byte = (ECLKDIV-1); /* ECLKx2 on. ECLK/(ECLKDIV) on */
426: // ECLKCTL.byte = (ECLKDIV-1)|DIV16; /* ECLKx2 on. ECLK/(ECLKDIV*16) on */
427:
428:
429: #endif
430: }
0115 0a [7] RTC
431:
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