s12iicv3.h

freescale 协处理器应用相关实例

/****************************************************************************
                                                 COPYRIGHT (c) Freescale 2005  
                                                                           
 File Name          :    $RCSfile: S12IICV3.h,v $                          
                                                                           
 Current Revision :      $Revision: 1.0 $                                  
                                                                           
 PURPOSE: header file for HCS12X(E) IIC module                              
                                                                           
 DESCRIPTION:  Defines the IIC register block as a datastructure of type tIIC.       
                                                                            
 UPDATE HISTORY                                                            
 REV  AUTHOR       DATE        DESCRIPTION OF CHANGE                       
 ---  ------       --------    ---------------------                       
 1.0  r32151    01/09/05    Initial Coding based on S12IICV2.h


     *******************************************************************
     * File created by: Freescale East Kilbride MCD Applications Group *
     *******************************************************************

                                                                          
******************************************************************************/
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#ifndef S12IICV3_H         /*prevent duplicated includes */
#define S12IICV3_H

#include "S12_COMMON.h"

typedef union uIBAD
  {
  tU08   byte;
  struct
    {
    tU08       :1;
    tU08 adr   :7;      /*slave address bits */
    }bit;
  }tIBAD;

/*bit masks for IBAD */
#define ADR1   0x02  
#define ADR2   0x04
#define ADR3   0x08
#define ADR4   0x10
#define ADR5   0x20
#define ADR6   0x40
#define ADR7   0x80

typedef union uIBFD
  {
  tU08   byte;
  struct
    {
    tU08 ibc   :8;      /*iic bus clock rate bits */
    }bit;
  }tIBFD;

/*bit masks for IBFD */
#define IBC0   0x01  
#define IBC1   0x02
#define IBC2   0x04
#define IBC3   0x08
#define IBC4   0x10
#define IBC5   0x20
#define IBC6   0x40
#define IBC7   0x80

typedef union uIBCR
  {
  tU08   byte;
  struct
    {
    tU08 ibswai :1;      /*iic stops in wait mode */
    tU08        :1;      /*not used */
    tU08 rsta   :1;      /*repeat start */
    tU08 txak   :1;      /*transmit acknowledge enable */
    tU08 txrx   :1;      /*transmit/receive mode select */
    tU08 mssl   :1;      /*master/slave mode select */
    tU08 ibie   :1;      /*iic bus interrupt enable */
    tU08 iben   :1;      /*iic bus enable */
    }bit;
  }tIBCR;

/*bit masks for IBCR */
#define IBSWAI 0x01  
#define RSTA   0x04
#define TXAK   0x08
#define TXRX   0x10
#define MSSL   0x20
#define IBIE   0x40
#define IBEN   0x80

typedef union uIBSR
  {
  tU08   byte;
  struct
    {
    tU08 rxak  :1;      /*received acknowledge */
    tU08 ibif  :1;      /*iic bus interrupt flag */
    tU08 srw   :1;      /*slave read/write */
    tU08       :1;      /*not used */
    tU08 ibal  :1;      /*arbitration lost */
    tU08 ibb   :1;      /*iic busy bit */
    tU08 iaas  :1;      /*addressed as a slave bit */
    tU08 tcf   :1;      /*data transferring bit */
    }bit;
  }tIBSR;

/*bit masks for IBSR */
#define RXAK   0x01  
#define IBIF   0x02
#define SRW    0x04
#define IBAL   0x10
#define IBB    0x20
#define IAAS   0x40
#define TCF    0x80

typedef union uIBCR2
  {
  tU08   byte;
  struct
    {
    tU08 ad     :3;      /*upper bits of 10-bit address */
    tU08        :3;      /*not used */
    tU08 adtype :1;      /*10-bit address enable */
    tU08 gca    :1;      /*general call address enable */
    }bit;
  }tIBCR2;

/*bit masks for IBCR2 */
#define ADTYPE   0x40
#define GCAEN    0x80


typedef struct          
  {
  volatile tIBAD  ibad;   /*iic bus address register */
  volatile tIBFD  ibfd;   /*iic bus frequency divider register */
  volatile tIBCR  ibcr;   /*iic bus control register */
  volatile tIBSR  ibsr;   /*iic bus status register */
  volatile tREG08 ibdr;   /*iic bus data register */
  volatile tIBCR2 ibcr2;  /*iic bus control register 2*/
           tU08   rsv[2]; /*reserved to complete module memory map */
  }tIIC;

#endif /*S12IICV3_H */