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📄 s12xgatev3.h

📁 freescale 协处理器应用相关实例
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               tU08 XGIF_24     :1;																			 /* Channel  36 (Hex24) corresponds to HCS12X Vector  91 at 0xFF48 */
               tU08 XGIF_25     :1;																			 /* Channel  37 (Hex25) corresponds to HCS12X Vector  90 at 0xFF4A */
               tU08 XGIF_26     :1;																			 /* Channel  38 (Hex26) corresponds to HCS12X Vector  89 at 0xFF4C */
               tU08 XGIF_27     :1;																			 /* Channel  39 (Hex27) corresponds to HCS12X Vector  88 at 0xFF4E */
            } bits_20_27;
            struct {
               tU08 XGIF_18     :1;																			 /* Channel  24 (Hex18) corresponds to HCS12X Vector 103 at 0xFF30 */
               tU08 XGIF_19     :1;																			 /* Channel  25 (Hex19) corresponds to HCS12X Vector 102 at 0xFF32 */
               tU08 XGIF_1A     :1;																			 /* Channel  26 (Hex1A) corresponds to HCS12X Vector 101 at 0xFF34 */
               tU08 XGIF_1B     :1;																			 /* Channel  27 (Hex1B) corresponds to HCS12X Vector 100 at 0xFF36 */
               tU08 XGIF_1C     :1;																			 /* Channel  28 (Hex1C) corresponds to HCS12X Vector  99 at 0xFF38 */
               tU08 XGIF_1D     :1;																			 /* Channel  29 (Hex1D) corresponds to HCS12X Vector  98 at 0xFF3A */
               tU08 XGIF_1E     :1;																			 /* Channel  30 (Hex1E) corresponds to HCS12X Vector  97 at 0xFF3C */
               tU08 XGIF_1F     :1;																			 /* Channel  31 (Hex1F) corresponds to HCS12X Vector  96 at 0xFF3E */
            } bbits_18_1F;
            struct {
               tU08 XGIF_10     :1;																			 /* Channel  16 (Hex10) corresponds to HCS12X Vector 111 at 0xFF20 */
               tU08 XGIF_11     :1;																			 /* Channel  17 (Hex11) corresponds to HCS12X Vector 110 at 0xFF22 */
               tU08 XGIF_12     :1;																			 /* Channel  18 (Hex12) corresponds to HCS12X Vector 109 at 0xFF24 */
               tU08 XGIF_13     :1;																			 /* Channel  19 (Hex13) corresponds to HCS12X Vector 108 at 0xFF26 */
               tU08 XGIF_14     :1;																			 /* Channel  20 (Hex14) corresponds to HCS12X Vector 107 at 0xFF28 */
               tU08 XGIF_15     :1;																			 /* Channel  21 (Hex15) corresponds to HCS12X Vector 106 at 0xFF2A */
               tU08 XGIF_16     :1;																			 /* Channel  22 (Hex16) corresponds to HCS12X Vector 105 at 0xFF2C */
               tU08 XGIF_17     :1;																			 /* Channel  23 (Hex17) corresponds to HCS12X Vector 104 at 0xFF2E */
            } bits_10_17;
            struct {
               tU08 XGIF_08     :1;																			 /* Channel   8 (Hex08) corresponds to HCS12X Vector 119 at 0xFF10 */
               tU08 XGIF_09     :1;																			 /* Channel   9 (Hex09) corresponds to HCS12X Vector 118 at 0xFF12 */
               tU08 XGIF_0A     :1;																			 /* Channel  10 (Hex0A) corresponds to HCS12X Vector 117 at 0xFF14 */
               tU08 XGIF_0B     :1;																			 /* Channel  11 (Hex0B) corresponds to HCS12X Vector 116 at 0xFF16 */
               tU08 XGIF_0C     :1;																			 /* Channel  12 (Hex0C) corresponds to HCS12X Vector 115 at 0xFF18 */
               tU08 XGIF_0D     :1;																			 /* Channel  13 (Hex0D) corresponds to HCS12X Vector 114 at 0xFF1A */
               tU08 XGIF_0E     :1;																			 /* Channel  14 (Hex0E) corresponds to HCS12X Vector 113 at 0xFF1C */
               tU08 XGIF_0F     :1;																			 /* Channel  15 (Hex0F) corresponds to HCS12X Vector 112 at 0xFF1E */
            } bits_08_0F;
            struct {
               tU08 XGIF_00     :1;																			 /* Channel   0 (Hex00) corresponds to HCS12X Vector 127 at 0xFF00 */
               tU08 XGIF_01     :1;																			 /* Channel   1 (Hex01) corresponds to HCS12X Vector 126 at 0xFF02 */
               tU08 XGIF_02     :1;																			 /* Channel   2 (Hex02) corresponds to HCS12X Vector 125 at 0xFF04 */
               tU08 XGIF_03     :1;																			 /* Channel   3 (Hex03) corresponds to HCS12X Vector 124 at 0xFF06 */
               tU08 XGIF_04     :1;																			 /* Channel   4 (Hex04) corresponds to HCS12X Vector 123 at 0xFF08 */
               tU08 XGIF_05     :1;																			 /* Channel   5 (Hex05) corresponds to HCS12X Vector 122 at 0xFF0A */
               tU08 XGIF_06     :1;																			 /* Channel   6 (Hex06) corresponds to HCS12X Vector 121 at 0xFF0C */
               tU08 XGIF_07     :1;																			 /* Channel   7 (Hex07) corresponds to HCS12X Vector 120 at 0xFF0E */
            } bits_00_07;
         } bit;
} tXGIF;

#define _7F_70    word[0]
#define _6F_60    word[1]
#define _5F_50    word[2]
#define _4F_40    word[3]
#define _3F_30    word[4]
#define _2F_20    word[5]
#define _1F_10    word[6]
#define _0F_00    word[7]

#define _7F_78    byte[ 0]
#define _77_70    byte[ 1]
#define _6F_68    byte[ 2]
#define _67_60    byte[ 3]
#define _5F_58    byte[ 4]
#define _57_50    byte[ 5]
#define _4F_48    byte[ 6]
#define _47_40    byte[ 7]
#define _3F_38    byte[ 8]
#define _37_30    byte[ 9]
#define _2F_28    byte[10]
#define _27_20    byte[11]
#define _1F_18    byte[12]
#define _17_10    byte[13]
#define _0F_08    byte[14]
#define _07_00    byte[15]

/* definitions to support previous header file versions */
#define xgif_70 xgif.word[0]       /* XGATE Channel Interrupt Flag 70 - 78 */
#define xgif_60 xgif.word[1]       /* XGATE Channel Interrupt Flag 60 - 6F */
#define xgif_50 xgif.word[2]       /* XGATE Channel Interrupt Flag 50 - 5F */				 
#define xgif_40 xgif.word[3]       /* XGATE Channel Interrupt Flag 40 - 4F */
#define xgif_30 xgif.word[4]       /* XGATE Channel Interrupt Flag 30 - 3F */
#define xgif_20 xgif.word[5]       /* XGATE Channel Interrupt Flag 20 - 2F */
#define xgif_10 xgif.word[6]       /* XGATE Channel Interrupt Flag 10 - 1F */
#define xgif_00 xgif.word[7]       /* XGATE Channel Interrupt Flag 09 - 0F */


typedef union uXGSWT
{
  tU16  word;
  struct
  {
    tU08 xgswtm;        /* XGATE Software Trigger Mask Register */
    tU08 xgswtr;        /* XGATE Software Trigger Register */
  }byte;
}tXGSWT;

/*bit masks for XGSWT  */
#define XGSWTM0 0x0100
#define XGSWTM1 0x0200
#define XGSWTM2 0x0400
#define XGSWTM3 0x0800
#define XGSWTM4 0x1000
#define XGSWTM5 0x2000
#define XGSWTM6 0x4000
#define XGSWTM7 0x8000

/* alternative mask bit defines for XGSWT*/
#define XGSWT0M 0x0100
#define XGSWT1M 0x0200
#define XGSWT2M 0x0400
#define XGSWT3M 0x0800
#define XGSWT4M 0x1000
#define XGSWT5M 0x2000
#define XGSWT6M 0x4000
#define XGSWT7M 0x8000

#define XGSWT0 0x01
#define XGSWT1 0x02
#define XGSWT2 0x04
#define XGSWT3 0x08
#define XGSWT4 0x10
#define XGSWT5 0x20
#define XGSWT6 0x40
#define XGSWT7 0x80

#define SWI0_MASK (XGSWT0|XGSWT0M)
#define SWI1_MASK (XGSWT1|XGSWT1M)
#define SWI2_MASK (XGSWT2|XGSWT2M)
#define SWI3_MASK (XGSWT3|XGSWT3M)
#define SWI4_MASK (XGSWT4|XGSWT4M)
#define SWI5_MASK (XGSWT5|XGSWT5M)
#define SWI6_MASK (XGSWT6|XGSWT6M)
#define SWI7_MASK (XGSWT7|XGSWT7M)

#define TRIGGER_SWI(x) 	XGATE.xgswt.word=(x)

typedef union uXGSEM
{
  tU16  word;
  struct
  {
    tU08 xgsemm;        /* XGATE Semaphore Mask Register */
    tU08 xgsemr;        /* XGATE Semaphore Register */
  }byte;
}tXGSEM;

/*bit masks for XGSEM */
#define XGSEMM0 0x0100
#define XGSEMM1 0x0200
#define XGSEMM2 0x0400
#define XGSEMM3 0x0800
#define XGSEMM4 0x1000
#define XGSEMM5 0x2000
#define XGSEMM6 0x4000
#define XGSEMM7 0x8000

/* alternative mask bit defines for XGSEM */
#define XGSEM0M 0x0100
#define XGSEM1M 0x0200
#define XGSEM2M 0x0400
#define XGSEM3M 0x0800
#define XGSEM4M 0x1000
#define XGSEM5M 0x2000
#define XGSEM6M 0x4000
#define XGSEM7M 0x8000

#define XGSEM0 0x01
#define XGSEM1 0x02
#define XGSEM2 0x04
#define XGSEM3 0x08
#define XGSEM4 0x10
#define XGSEM5 0x20
#define XGSEM6 0x40
#define XGSEM7 0x80

typedef union uXGCCR
{
  tU08   byte;
  struct
  {
    tU08 xgc   :1;      /* XGATE Carry Flag */
    tU08 xgv   :1;      /* XGATE Overflow Flag */
    tU08 xgz   :1;      /* XGATE Zero Flag */
    tU08 xgn   :1;      /* XGATE Sign Flag */
    tU08       :4;      /* not used */
  }bit;
}tXGCCR;


typedef struct             /* XGATE module used on the S12XDP256  */
{
  volatile tU16         xgmctl;        /* XGATE Module Control Register */
  volatile tU08         xgchid;        /* XGATE Channel ID Register     */
  volatile tXGCHPL		xgchpl;			/* XGATE channel priority level */
           tU08         rsv0;          /* reserved */
  volatile tXGISPSEL		xgispsel;		/* XGATE initial stack pointer select register */
  volatile tU16         xgvbr;         /* XGATE Vector Base Address Register */  
  volatile tXGIF        xgif;          /* XGATE Channel Interrupt Flag 70 - 78 */
  volatile tXGSWT       xgswt;         /* XGATE Software Trigger Register */
  volatile tXGSEM       xgsem;         /* XGATE Semaphore Register */
           tU08         rsv1c;         /* reserved byte */
  volatile tXGCCR       xgccr;         /* XGATE Condition Code Register */
  volatile tU16         xgpc;          /* XGATE Program Counter */
           tU16         rsv20;         /* reserved word */
  volatile tU16         xgr1;          /* XGATE Register 1 */
  volatile tU16         xgr2;          /* XGATE Register 2 */
  volatile tU16         xgr3;          /* XGATE Register 3 */
  volatile tU16         xgr4;          /* XGATE Register 4 */
  volatile tU16         xgr5;          /* XGATE Register 5 */
  volatile tU16         xgr6;          /* XGATE Register 6 */
  volatile tU16         xgr7;          /* XGATE Register 7 */
}tXGATE;

#endif /* S12XGATEV3_H  */

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