xgate_channels_m22h.h

freescale 协处理器应用相关实例

#define XGIF_MASK_SCI3        (0x0001<<0x04)  // Channel 44 - SCI3                     
#define XGIF_MASK_SCI2        (0x0001<<0x05)  // Channel 45 - SCI2                     
#define XGIF_MASK_PWMES       (0x0001<<0x06)  // Channel 46 - PWM Emergency Shutdown   
#define XGIF_MASK_PTP         (0x0001<<0x07)  // Channel 47 - Port P Interrupt         
#define XGIF_MASK_CAN4TX      (0x0001<<0x08)  // Channel 48 - CAN4 transmit            
#define XGIF_MASK_CAN4RX      (0x0001<<0x09)  // Channel 49 - CAN4 receive             
#define XGIF_MASK_CAN4ERR     (0x0001<<0x0A)  // Channel 4A - CAN4 errors              
#define XGIF_MASK_CAN4WUP     (0x0001<<0x0B)  // Channel 4B - CAN4 wake-up             
#define XGIF_MASK_CAN3TX      (0x0001<<0x0C)  // Channel 4C - CAN3 transmit            
#define XGIF_MASK_CAN3RX      (0x0001<<0x0D)  // Channel 4D - CAN3 receive             
#define XGIF_MASK_CAN3ERR     (0x0001<<0x0E)  // Channel 4E - CAN3 errors              
#define XGIF_MASK_CAN3WUP     (0x0001<<0x0F)  // Channel 4F - CAN3 wake-up             
#define XGIF_MASK_CAN2TX       0x0001         // Channel 50 - CAN2 transmit
#define XGIF_MASK_CAN2RX      (0x0001<<0x01)  // Channel 51 - CAN2 receive 
#define XGIF_MASK_CAN2ERR     (0x0001<<0x02)  // Channel 52 - CAN2 errors  
#define XGIF_MASK_CAN2WUP     (0x0001<<0x03)  // Channel 53 - CAN2 wake-up 
#define XGIF_MASK_CAN1TX      (0x0001<<0x04)  // Channel 54 - CAN1 transmit
#define XGIF_MASK_CAN1RX      (0x0001<<0x05)  // Channel 55 - CAN1 receive 
#define XGIF_MASK_CAN1ERR     (0x0001<<0x06)  // Channel 56 - CAN1 errors  
#define XGIF_MASK_CAN1WUP     (0x0001<<0x07)  // Channel 57 - CAN1 wake-up 
#define XGIF_MASK_CAN0TX      (0x0001<<0x08)  // Channel 58 - CAN0 transmit
#define XGIF_MASK_CAN0RX      (0x0001<<0x09)  // Channel 59 - CAN0 receive 
#define XGIF_MASK_CAN0ERR     (0x0001<<0x0A)  // Channel 5A - CAN0 errors  
#define XGIF_MASK_CAN0WUP     (0x0001<<0x0B)  // Channel 5B - CAN0 wake-up 
#define XGIF_MASK_FLASH       (0x0001<<0x0C)  // Channel 5C - FLASH 
#define XGIF_MASK_FLASH_FAULT (0x0001<<0x0D)  // Channel 5D - FLASH fault detect
#define XGIF_MASK_SPI2        (0x0001<<0x0E)  // Channel 5E - SPI2  
#define XGIF_MASK_SPI1        (0x0001<<0x0F)  // Channel 5F - SPI1
#define XGIF_MASK_IIC0         0x0001         // Channel 60 - IIC0 Bus                         
#define XGIF_MASK_SCI6        (0x0001<<0x01)  // Channel 61 - SCI6                         
#define XGIF_MASK_SCM         (0x0001<<0x02)  // Channel 62 - CRG Self Clock Mode              
#define XGIF_MASK_PLLLOCK     (0x0001<<0x03)  // Channel 63 - CRG PLL lock                     
#define XGIF_MASK_PACBOF      (0x0001<<0x04)  // Channel 64 - Pulse Accumulator B Overflow     
#define XGIF_MASK_MODUF       (0x0001<<0x05)  // Channel 65 - Modulus Down Counter underflow   
#define XGIF_MASK_PTH         (0x0001<<0x06)  // Channel 66 - Port H                           
#define XGIF_MASK_PTJ         (0x0001<<0x07)  // Channel 67 - Port J                           
#define XGIF_MASK_ATD1        (0x0001<<0x08)  // Channel 68 - ATD1                             
#define XGIF_MASK_ADT0        (0x0001<<0x09)  // Channel 69 - ATD0                             
#define XGIF_MASK_SCI1        (0x0001<<0x0A)  // Channel 6A - SCI1                             
#define XGIF_MASK_SCI0        (0x0001<<0x0B)  // Channel 6B - SCI0                             
#define XGIF_MASK_SPI0        (0x0001<<0x0C)  // Channel 6C - SPI0                             
#define XGIF_MASK_ECT_PACIPE  (0x0001<<0x0D)  // Channel 6D - Pulse accumulator input edge     
#define XGIF_MASK_ECT_PACAOF  (0x0001<<0x0E)  // Channel 6E - Pulse accumulator A overflow     
#define XGIF_MASK_ECTOF       (0x0001<<0x0F)  // Channel 6F - Enhanced Capture Timer overflow  
#define XGIF_MASK_ECTCH7       0x0001         // Channel 70 - Enhanced Capture Timer channel 7                                 
#define XGIF_MASK_ECTCH6      (0x0001<<0x01)  // Channel 71 - Enhanced Capture Timer channel 6 
#define XGIF_MASK_ECTCH5      (0x0001<<0x02)  // Channel 72 - Enhanced Capture Timer channel 5 
#define XGIF_MASK_ECTCH4      (0x0001<<0x03)  // Channel 73 - Enhanced Capture Timer channel 4 
#define XGIF_MASK_ECTCH3      (0x0001<<0x04)  // Channel 74 - Enhanced Capture Timer channel 3 
#define XGIF_MASK_ECTCH2      (0x0001<<0x05)  // Channel 75 - Enhanced Capture Timer channel 2 
#define XGIF_MASK_ECTCH1      (0x0001<<0x06)  // Channel 76 - Enhanced Capture Timer channel 1 
#define XGIF_MASK_ECTCH0      (0x0001<<0x07)  // Channel 77 - Enhanced Capture Timer channel 0 
#define XGIF_MASK_RTI         (0x0001<<0x08)  // Channel 78 - Real Time Interrupt 

/* XGate channel bit name */
#define XGIF_ATD1CMP     XGIF_1E  // Channel 1E - ATD1 compare                            
#define XGIF_ADT0CMP     XGIF_1F  // Channel 1F - ATD0 compare                            
#define XGIF_TIM_PACIPE  XGIF_20  // Channel 20 - TIM Pulse accumulator input edge     
#define XGIF_TIM_PACAOF  XGIF_21  // Channel 21 - TIM Pulse accumulator A overflow     
#define XGIF_TIMOF       XGIF_22  // Channel 22 - TIM overflow  
#define XGIF_TIMCH7      XGIF_23  // Channel 23 - TIM channel 7                                 
#define XGIF_TIMCH6      XGIF_24  // Channel 24 - TIM channel 6 
#define XGIF_TIMCH5      XGIF_25  // Channel 25 - TIM channel 5 
#define XGIF_TIMCH4      XGIF_26  // Channel 26 - TIM channel 4 
#define XGIF_TIMCH3      XGIF_27  // Channel 27 - TIM channel 3 
#define XGIF_TIMCH2      XGIF_28  // Channel 28 - TIM channel 2 
#define XGIF_TIMCH1      XGIF_29  // Channel 29 - TIM channel 1 
#define XGIF_TIMCH0      XGIF_2A  // Channel 2A - TIM channel 0 
#define XGIF_SCI7        XGIF_2B  // Channel 2B - SCI7                     
#define XGIF_PITCH7      XGIF_2C  // Channel 2C - Periodic Interrupt Timer 7          
#define XGIF_PITCH6      XGIF_2D  // Channel 2D - Periodic Interrupt Timer 6          
#define XGIF_PITCH5      XGIF_2E  // Channel 2E - Periodic Interrupt Timer 5          
#define XGIF_PITCH4      XGIF_2F  // Channel 2F - Periodic Interrupt Timer 4          
//#define XGIF_          XGIF_30  // Channel 30 - Reserved                         
//#define XGIF_          XGIF_31  // Channel 31 - Reserved                         
#define XGIF_SWI7        XGIF_32  // Channel 32 - XGATE Software Trigger 7           
#define XGIF_SWI6        XGIF_33  // Channel 33 - XGATE Software Trigger 6           
#define XGIF_SWI5        XGIF_34  // Channel 34 - XGATE Software Trigger 5           
#define XGIF_SWI4        XGIF_35  // Channel 35 - XGATE Software Trigger 4           
#define XGIF_SWI3        XGIF_36  // Channel 36 - XGATE Software Trigger 3           
#define XGIF_SWI2        XGIF_37  // Channel 37 - XGATE Software Trigger 2           
#define XGIF_SWI1        XGIF_38  // Channel 38 - XGATE Software Trigger 1           
#define XGIF_SWI0        XGIF_39  // Channel 39 - XGATE Software Trigger 0           
#define XGIF_PITCH3      XGIF_3A  // Channel 3A - Periodic Interrupt Timer 3          
#define XGIF_PITCH2      XGIF_3B  // Channel 3B - Periodic Interrupt Timer 2          
#define XGIF_PITCH1      XGIF_3C  // Channel 3C - Periodic Interrupt Timer 1          
#define XGIF_PITCH0      XGIF_3D  // Channel 3D - Periodic Interrupt Timer 0          
//#define XGIF_          XGIF_3E  // Channel 3E - Reserved                         
#define XGIF_API         XGIF_3F  // Channel 3F - Autonomous Periodical interrupt API
#define XGIF_LVI         XGIF_40  // Channel 40 - Low Voltage interrupt LVI
#define XGIF_IIC1        XGIF_41  // Channel 41 - IIC1 Bus                 
#define XGIF_SCI5        XGIF_42  // Channel 42 - SCI5                     
#define XGIF_SCI4        XGIF_43  // Channel 43 - SCI4                     
#define XGIF_SCI3        XGIF_44  // Channel 44 - SCI3                     
#define XGIF_SCI2        XGIF_45  // Channel 45 - SCI2                     
#define XGIF_PWMES       XGIF_46  // Channel 46 - PWM Emergency Shutdown   
#define XGIF_PTP         XGIF_47  // Channel 47 - Port P Interrupt         
#define XGIF_CAN4TX      XGIF_48  // Channel 48 - CAN4 transmit            
#define XGIF_CAN4RX      XGIF_49  // Channel 49 - CAN4 receive             
#define XGIF_CAN4ERR     XGIF_4A  // Channel 4A - CAN4 errors              
#define XGIF_CAN4WUP     XGIF_4B  // Channel 4B - CAN4 wake-up             
#define XGIF_CAN3TX      XGIF_4C  // Channel 4C - CAN3 transmit            
#define XGIF_CAN3RX      XGIF_4D  // Channel 4D - CAN3 receive             
#define XGIF_CAN3ERR     XGIF_4E  // Channel 4E - CAN3 errors              
#define XGIF_CAN3WUP     XGIF_4F  // Channel 4F - CAN3 wake-up             
#define XGIF_CAN2TX      XGIF_50  // Channel 50 - CAN2 transmit
#define XGIF_CAN2RX      XGIF_51  // Channel 51 - CAN2 receive 
#define XGIF_CAN2ERR     XGIF_52  // Channel 52 - CAN2 errors  
#define XGIF_CAN2WUP     XGIF_53  // Channel 53 - CAN2 wake-up 
#define XGIF_CAN1TX      XGIF_54  // Channel 54 - CAN1 transmit
#define XGIF_CAN1RX      XGIF_55  // Channel 55 - CAN1 receive 
#define XGIF_CAN1ERR     XGIF_56  // Channel 56 - CAN1 errors  
#define XGIF_CAN1WUP     XGIF_57  // Channel 57 - CAN1 wake-up 
#define XGIF_CAN0TX      XGIF_58  // Channel 58 - CAN0 transmit
#define XGIF_CAN0RX      XGIF_59  // Channel 59 - CAN0 receive 
#define XGIF_CAN0ERR     XGIF_5A  // Channel 5A - CAN0 errors  
#define XGIF_CAN0WUP     XGIF_5B  // Channel 5B - CAN0 wake-up 
#define XGIF_FLASH       XGIF_5C  // Channel 5C - FLASH 
#define XGIF_FLASH_FAULT XGIF_5D  // Channel 5D - FLASH fault detect
#define XGIF_SPI2        XGIF_5E  // Channel 5E - SPI2  
#define XGIF_SPI1        XGIF_5F  // Channel 5F - SPI1
#define XGIF_IIC0        XGIF_60  // Channel 60 - IIC0 Bus                         
#define XGIF_SCI6        XGIF_61  // Channel 61 - SCI6                         
#define XGIF_SCM         XGIF_62  // Channel 62 - CRG Self Clock Mode              
#define XGIF_PLLLOCK     XGIF_63  // Channel 63 - CRG PLL lock                     
#define XGIF_PACBOF      XGIF_64  // Channel 64 - Pulse Accumulator B Overflow     
#define XGIF_MODUF       XGIF_65  // Channel 65 - Modulus Down Counter underflow   
#define XGIF_PTH         XGIF_66  // Channel 66 - Port H                           
#define XGIF_PTJ         XGIF_67  // Channel 67 - Port J                           
#define XGIF_ATD1        XGIF_68  // Channel 68 - ATD1                             
#define XGIF_ADT0        XGIF_69  // Channel 69 - ATD0                             
#define XGIF_SCI1        XGIF_6A  // Channel 6A - SCI1                             
#define XGIF_SCI0        XGIF_6B  // Channel 6B - SCI0                             
#define XGIF_SPI0        XGIF_6C  // Channel 6C - SPI0                             
#define XGIF_ECT_PACIPE  XGIF_6D  // Channel 6D - Pulse accumulator input edge     
#define XGIF_ECT_PACAOF  XGIF_6E  // Channel 6E - Pulse accumulator A overflow     
#define XGIF_ECTOF       XGIF_6F  // Channel 6F - Enhanced Capture Timer overflow  
#define XGIF_ECTCH7      XGIF_70  // Channel 70 - Enhanced Capture Timer channel 7                                 
#define XGIF_ECTCH6      XGIF_71  // Channel 71 - Enhanced Capture Timer channel 6 
#define XGIF_ECTCH5      XGIF_72  // Channel 72 - Enhanced Capture Timer channel 5 
#define XGIF_ECTCH4      XGIF_73  // Channel 73 - Enhanced Capture Timer channel 4 
#define XGIF_ECTCH3      XGIF_74  // Channel 74 - Enhanced Capture Timer channel 3 
#define XGIF_ECTCH2      XGIF_75  // Channel 75 - Enhanced Capture Timer channel 2 
#define XGIF_ECTCH1      XGIF_76  // Channel 76 - Enhanced Capture Timer channel 1 
#define XGIF_ECTCH0      XGIF_77  // Channel 77 - Enhanced Capture Timer channel 0 
#define XGIF_RTI         XGIF_78  // Channel 78 - Real Time Interrupt 

#endif XGIF_H