xgate_channels_m22h.h

freescale 协处理器应用相关实例

#define XGCHID_ATD1        0x68  // Channel 68 - ATD1                             
#define XGCHID_ADT0        0x69  // Channel 69 - ATD0                             
#define XGCHID_SCI1        0x6A  // Channel 6A - SCI1                             
#define XGCHID_SCI0        0x6B  // Channel 6B - SCI0                             
#define XGCHID_SPI0        0x6C  // Channel 6C - SPI0                             
#define XGCHID_ECT_PACIPE  0x6D  // Channel 6D - Pulse accumulator input edge     
#define XGCHID_ECT_PACAOF  0x6E  // Channel 6E - Pulse accumulator A overflow     
#define XGCHID_ECTOF       0x6F  // Channel 6F - Enhanced Capture Timer overflow  
#define XGCHID_ECTCH7      0x70  // Channel 70 - Enhanced Capture Timer channel 7                                 
#define XGCHID_ECTCH6      0x71  // Channel 71 - Enhanced Capture Timer channel 6 
#define XGCHID_ECTCH5      0x72  // Channel 72 - Enhanced Capture Timer channel 5 
#define XGCHID_ECTCH4      0x73  // Channel 73 - Enhanced Capture Timer channel 4 
#define XGCHID_ECTCH3      0x74  // Channel 74 - Enhanced Capture Timer channel 3 
#define XGCHID_ECTCH2      0x75  // Channel 75 - Enhanced Capture Timer channel 2 
#define XGCHID_ECTCH1      0x76  // Channel 76 - Enhanced Capture Timer channel 1 
#define XGCHID_ECTCH0      0x77  // Channel 77 - Enhanced Capture Timer channel 0 
#define XGCHID_RTI         0x78  // Channel 78 - Real Time Interrupt 

/* XGate Interrupt Flag word identifier */
#define XGIF_WORD_ATD1CMP     xgif_10 // Channel 1E - ATD1 compare                            
#define XGIF_WORD_ADT0CMP     xgif_10 // Channel 1F - ATD0 compare                            
#define XGIF_WORD_TIM_PACIPE  xgif_20 // Channel 20 - TIM Pulse accumulator input edge     
#define XGIF_WORD_TIM_PACAOF  xgif_20 // Channel 21 - TIM Pulse accumulator A overflow     
#define XGIF_WORD_TIMOF       xgif_20 // Channel 22 - TIM overflow  
#define XGIF_WORD_TIMCH7      xgif_20 // Channel 23 - TIM channel 7                                 
#define XGIF_WORD_TIMCH6      xgif_20 // Channel 24 - TIM channel 6 
#define XGIF_WORD_TIMCH5      xgif_20 // Channel 25 - TIM channel 5 
#define XGIF_WORD_TIMCH4      xgif_20 // Channel 26 - TIM channel 4 
#define XGIF_WORD_TIMCH3      xgif_20 // Channel 27 - TIM channel 3 
#define XGIF_WORD_TIMCH2      xgif_20 // Channel 28 - TIM channel 2 
#define XGIF_WORD_TIMCH1      xgif_20 // Channel 29 - TIM channel 1 
#define XGIF_WORD_TIMCH0      xgif_20 // Channel 2A - TIM channel 0 
#define XGIF_WORD_SCI7        xgif_20 // Channel 2B - SCI7                     
#define XGIF_WORD_PITCH7      xgif_20 // Channel 2C - Periodic Interrupt Timer 7          
#define XGIF_WORD_PITCH6      xgif_20 // Channel 2D - Periodic Interrupt Timer 6          
#define XGIF_WORD_PITCH5      xgif_20 // Channel 2E - Periodic Interrupt Timer 5          
#define XGIF_WORD_PITCH4      xgif_20 // Channel 2F - Periodic Interrupt Timer 4          
//#define XGIF_WORD_          xgif_30  // Channel 30 - Reserved                         
//#define XGIF_WORD_          xgif_30  // Channel 31 - Reserved                         
#define XGIF_WORD_SWI7        xgif_30  // Channel 32 - XGATE Software Trigger 7           
#define XGIF_WORD_SWI6        xgif_30  // Channel 33 - XGATE Software Trigger 6           
#define XGIF_WORD_SWI5        xgif_30  // Channel 34 - XGATE Software Trigger 5           
#define XGIF_WORD_SWI4        xgif_30  // Channel 35 - XGATE Software Trigger 4           
#define XGIF_WORD_SWI3        xgif_30  // Channel 36 - XGATE Software Trigger 3           
#define XGIF_WORD_SWI2        xgif_30  // Channel 37 - XGATE Software Trigger 2           
#define XGIF_WORD_SWI1        xgif_30  // Channel 38 - XGATE Software Trigger 1           
#define XGIF_WORD_SWI0        xgif_30  // Channel 39 - XGATE Software Trigger 0           
#define XGIF_WORD_PITCH3      xgif_30  // Channel 3A - Periodic Interrupt Timer 3          
#define XGIF_WORD_PITCH2      xgif_30  // Channel 3B - Periodic Interrupt Timer 2          
#define XGIF_WORD_PITCH1      xgif_30  // Channel 3C - Periodic Interrupt Timer 1          
#define XGIF_WORD_PITCH0      xgif_30  // Channel 3D - Periodic Interrupt Timer 0          
//#define XGIF_WORD_          xgif_30  // Channel 3E - Reserved                         
#define XGIF_WORD_API         xgif_30  // Channel 3F - Autonomous Periodical interrupt API
#define XGIF_WORD_LVI         xgif_40  // Channel 40 - Low Voltage interrupt LVI
#define XGIF_WORD_IIC1        xgif_40  // Channel 41 - IIC1 Bus                 
#define XGIF_WORD_SCI5        xgif_40  // Channel 42 - SCI5                     
#define XGIF_WORD_SCI4        xgif_40  // Channel 43 - SCI4                     
#define XGIF_WORD_SCI3        xgif_40  // Channel 44 - SCI3                     
#define XGIF_WORD_SCI2        xgif_40  // Channel 45 - SCI2                     
#define XGIF_WORD_PWMES       xgif_40  // Channel 46 - PWM Emergency Shutdown   
#define XGIF_WORD_PTP         xgif_40  // Channel 47 - Port P Interrupt         
#define XGIF_WORD_CAN4TX      xgif_40  // Channel 48 - CAN4 transmit            
#define XGIF_WORD_CAN4RX      xgif_40  // Channel 49 - CAN4 receive             
#define XGIF_WORD_CAN4ERR     xgif_40  // Channel 4A - CAN4 errors              
#define XGIF_WORD_CAN4WUP     xgif_40  // Channel 4B - CAN4 wake-up             
#define XGIF_WORD_CAN3TX      xgif_40  // Channel 4C - CAN3 transmit            
#define XGIF_WORD_CAN3RX      xgif_40  // Channel 4D - CAN3 receive             
#define XGIF_WORD_CAN3ERR     xgif_40  // Channel 4E - CAN3 errors              
#define XGIF_WORD_CAN3WUP     xgif_40  // Channel 4F - CAN3 wake-up             
#define XGIF_WORD_CAN2TX      xgif_50  // Channel 50 - CAN2 transmit
#define XGIF_WORD_CAN2RX      xgif_50  // Channel 51 - CAN2 receive 
#define XGIF_WORD_CAN2ERR     xgif_50  // Channel 52 - CAN2 errors  
#define XGIF_WORD_CAN2WUP     xgif_50  // Channel 53 - CAN2 wake-up 
#define XGIF_WORD_CAN1TX      xgif_50  // Channel 54 - CAN1 transmit
#define XGIF_WORD_CAN1RX      xgif_50  // Channel 55 - CAN1 receive 
#define XGIF_WORD_CAN1ERR     xgif_50  // Channel 56 - CAN1 errors  
#define XGIF_WORD_CAN1WUP     xgif_50  // Channel 57 - CAN1 wake-up 
#define XGIF_WORD_CAN0TX      xgif_50  // Channel 58 - CAN0 transmit
#define XGIF_WORD_CAN0RX      xgif_50  // Channel 59 - CAN0 receive 
#define XGIF_WORD_CAN0ERR     xgif_50  // Channel 5A - CAN0 errors  
#define XGIF_WORD_CAN0WUP     xgif_50  // Channel 5B - CAN0 wake-up 
#define XGIF_WORD_FLASH       xgif_50  // Channel 5C - FLASH 
#define XGIF_WORD_FLASH_FAULT xgif_50  // Channel 5D - FLASH fault detect
#define XGIF_WORD_SPI2        xgif_50  // Channel 5E - SPI2  
#define XGIF_WORD_SPI1        xgif_50  // Channel 5F - SPI1
#define XGIF_WORD_IIC0        xgif_60  // Channel 60 - IIC0 Bus                         
#define XGIF_WORD_SCI6        xgif_60  // Channel 61 - SCI6                         
#define XGIF_WORD_SCM         xgif_60  // Channel 62 - CRG Self Clock Mode              
#define XGIF_WORD_PLLLOCK     xgif_60  // Channel 63 - CRG PLL lock                     
#define XGIF_WORD_PACBOF      xgif_60  // Channel 64 - Pulse Accumulator B Overflow     
#define XGIF_WORD_MODUF       xgif_60  // Channel 65 - Modulus Down Counter underflow   
#define XGIF_WORD_PTH         xgif_60  // Channel 66 - Port H                           
#define XGIF_WORD_PTJ         xgif_60  // Channel 67 - Port J                           
#define XGIF_WORD_ATD1        xgif_60  // Channel 68 - ATD1                             
#define XGIF_WORD_ADT0        xgif_60  // Channel 69 - ATD0                             
#define XGIF_WORD_SCI1        xgif_60  // Channel 6A - SCI1                             
#define XGIF_WORD_SCI0        xgif_60  // Channel 6B - SCI0                             
#define XGIF_WORD_SPI0        xgif_60  // Channel 6C - SPI0                             
#define XGIF_WORD_ECT_PACIPE  xgif_60  // Channel 6D - Pulse accumulator input edge     
#define XGIF_WORD_ECT_PACAOF  xgif_60  // Channel 6E - Pulse accumulator A overflow     
#define XGIF_WORD_ECTOF       xgif_60  // Channel 6F - Enhanced Capture Timer overflow  
#define XGIF_WORD_ECTCH7      xgif_70  // Channel 70 - Enhanced Capture Timer channel 7                                 
#define XGIF_WORD_ECTCH6      xgif_70  // Channel 71 - Enhanced Capture Timer channel 6 
#define XGIF_WORD_ECTCH5      xgif_70  // Channel 72 - Enhanced Capture Timer channel 5 
#define XGIF_WORD_ECTCH4      xgif_70  // Channel 73 - Enhanced Capture Timer channel 4 
#define XGIF_WORD_ECTCH3      xgif_70  // Channel 74 - Enhanced Capture Timer channel 3 
#define XGIF_WORD_ECTCH2      xgif_70  // Channel 75 - Enhanced Capture Timer channel 2 
#define XGIF_WORD_ECTCH1      xgif_70  // Channel 76 - Enhanced Capture Timer channel 1 
#define XGIF_WORD_ECTCH0      xgif_70  // Channel 77 - Enhanced Capture Timer channel 0 
#define XGIF_WORD_RTI         xgif_70  // Channel 78 - Real Time Interrupt 

/* XGate Interrupt Flag word bit masks */
#define XGIF_MASK_ATD1CMP     (0x0001<<0x0E)  // Channel 1E - ATD1 compare                            
#define XGIF_MASK_ADT0CMP     (0x0001<<0x0F)  // Channel 1F - ATD0 compare                            
#define XGIF_MASK_TIM_PACIPE   0x0001         // Channel 20 - TIM Pulse accumulator input edge     
#define XGIF_MASK_TIM_PACAOF  (0x0001<<0x01)  // Channel 21 - TIM Pulse accumulator A overflow     
#define XGIF_MASK_TIMOF       (0x0001<<0x02)  // Channel 22 - TIM overflow  
#define XGIF_MASK_TIMCH7      (0x0001<<0x03)  // Channel 23 - TIM channel 7                                 
#define XGIF_MASK_TIMCH6      (0x0001<<0x04)  // Channel 24 - TIM channel 6 
#define XGIF_MASK_TIMCH5      (0x0001<<0x05)  // Channel 25 - TIM channel 5 
#define XGIF_MASK_TIMCH4      (0x0001<<0x06)  // Channel 26 - TIM channel 4 
#define XGIF_MASK_TIMCH3      (0x0001<<0x07)  // Channel 27 - TIM channel 3 
#define XGIF_MASK_TIMCH2      (0x0001<<0x08)  // Channel 28 - TIM channel 2 
#define XGIF_MASK_TIMCH1      (0x0001<<0x09)  // Channel 29 - TIM channel 1 
#define XGIF_MASK_TIMCH0      (0x0001<<0x0A)  // Channel 2A - TIM channel 0 
#define XGIF_MASK_SCI7        (0x0001<<0x0B)  // Channel 2B - SCI7                     
#define XGIF_MASK_PITCH7      (0x0001<<0x0C)  // Channel 2C - Periodic Interrupt Timer 7          
#define XGIF_MASK_PITCH6      (0x0001<<0x0D)  // Channel 2D - Periodic Interrupt Timer 6          
#define XGIF_MASK_PITCH5      (0x0001<<0x0E)  // Channel 2E - Periodic Interrupt Timer 5          
#define XGIF_MASK_PITCH4      (0x0001<<0x0F)  // Channel 2F - Periodic Interrupt Timer 4          
//#define XGIF_MASK_           0x0001         // Channel 30 - Reserved                         
//#define XGIF_MASK_          (0x0001<<0x01)  // Channel 31 - Reserved                         
#define XGIF_MASK_SWI7        (0x0001<<0x02)  // Channel 32 - XGATE Software Trigger 7           
#define XGIF_MASK_SWI6        (0x0001<<0x03)  // Channel 33 - XGATE Software Trigger 6           
#define XGIF_MASK_SWI5        (0x0001<<0x04)  // Channel 34 - XGATE Software Trigger 5           
#define XGIF_MASK_SWI4        (0x0001<<0x05)  // Channel 35 - XGATE Software Trigger 4           
#define XGIF_MASK_SWI3        (0x0001<<0x06)  // Channel 36 - XGATE Software Trigger 3           
#define XGIF_MASK_SWI2        (0x0001<<0x07)  // Channel 37 - XGATE Software Trigger 2           
#define XGIF_MASK_SWI1        (0x0001<<0x08)  // Channel 38 - XGATE Software Trigger 1           
#define XGIF_MASK_SWI0        (0x0001<<0x09)  // Channel 39 - XGATE Software Trigger 0           
#define XGIF_MASK_PITCH3      (0x0001<<0x0A)  // Channel 3A - Periodic Interrupt Timer 3          
#define XGIF_MASK_PITCH2      (0x0001<<0x0B)  // Channel 3B - Periodic Interrupt Timer 2          
#define XGIF_MASK_PITCH1      (0x0001<<0x0C)  // Channel 3C - Periodic Interrupt Timer 1          
#define XGIF_MASK_PITCH0      (0x0001<<0x0D)  // Channel 3D - Periodic Interrupt Timer 0          
//#define XGIF_MASK_          (0x0001<<0x0E)  // Channel 3E - Reserved                         
#define XGIF_MASK_API         (0x0001<<0x0F)  // Channel 3F - Autonomous Periodical interrupt API
#define XGIF_MASK_LVI          0x0001         // Channel 40 - Low Voltage interrupt LVI
#define XGIF_MASK_IIC1        (0x0001<<0x01)  // Channel 41 - IIC1 Bus                 
#define XGIF_MASK_SCI5        (0x0001<<0x02)  // Channel 42 - SCI5                     
#define XGIF_MASK_SCI4        (0x0001<<0x03)  // Channel 43 - SCI4