xgate_channels_m22h.h

freescale 协处理器应用相关实例

/* XGate interrupt flag defines */

/******************************************************************************
													            Copyright (c) Freescale 2005
File Name	 :	$RCSfile: xgate_channels_M22H.h,v $

Engineer		 :	$Author: r32151 $

Location		 :	EKB

Date Created	  :	02/09/2005

Current Revision :	$Revision: 1.0 $

Notes            :   #defines for easy management of the banked XGate 
                     interrupt flags when using the EKB header files -
                     
                        to clear the xgate interrupt flag in mcu interrupt xyz:
                           XGATE.XGIF_WORD_XYZ = XGIF_MASK_XYZ;
                     
                        to check if the source of an mcu interrupt was 
                        the equivalent Xgate channel xyz:
                           if( XGATE.XGIF_WORD_XYZ & XGIF_MASK_XYZ )
                     
                     #defines of XGate channel IDs for use with the sif()
                     instruction.

                        to generate a specific mcu interrupt xyz:
                           sif( XGCHID_XYZ );

UPDATE HISTORY                                                            
REV  AUTHOR     DATE       DESCRIPTION OF CHANGE                          
---  ------    --------    ---------------------                          
1.0  r32151    02/09/05    - Adapted from xgate_channels_L15Y.h                      


     *******************************************************************
     * File created by: Freescale East Kilbride MCD Applications Group *
     *******************************************************************

                                                                          
******************************************************************************/
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#ifndef XGIF_H        /*prevent duplicated includes*/
#define XGIF_H

/************************* Macros ******************************************/

#define XGIF_CLEAR_CHANNEL_BIT(b)  { XGATE.xgif.byte[(XGATE_MAX_NUM_VECTOR - (b) - 1) >> 3]= (1U << ((b) & 0x7)); }
#define XGIF_READ_CHANNEL_BIT(b)   ((XGATE.xgif.byte[(XGATE_MAX_NUM_VECTOR - (b) - 1) >> 3] & (1U << ((b) & 0x7))) != 0)

/************************* #defines ******************************************/

#define XGATE_MAX_NUM_VECTOR 128

/* XGate channel identifier */
#define XGCHID_ATD1CMP     0x1E  // Channel 1E - ATD1 compare                            
#define XGCHID_ADT0CMP     0x1F  // Channel 1F - ATD0 compare                            
#define XGCHID_TIM_PACIPE  0x20  // Channel 20 - TIM Pulse accumulator input edge     
#define XGCHID_TIM_PACAOF  0x21  // Channel 21 - TIM Pulse accumulator A overflow     
#define XGCHID_TIMOF       0x22  // Channel 22 - TIM overflow  
#define XGCHID_TIMCH7      0x23  // Channel 23 - TIM channel 7                                 
#define XGCHID_TIMCH6      0x24  // Channel 24 - TIM channel 6 
#define XGCHID_TIMCH5      0x25  // Channel 25 - TIM channel 5 
#define XGCHID_TIMCH4      0x26  // Channel 26 - TIM channel 4 
#define XGCHID_TIMCH3      0x27  // Channel 27 - TIM channel 3 
#define XGCHID_TIMCH2      0x28  // Channel 28 - TIM channel 2 
#define XGCHID_TIMCH1      0x29  // Channel 29 - TIM channel 1 
#define XGCHID_TIMCH0      0x2A  // Channel 2A - TIM channel 0 
#define XGCHID_SCI7        0x2B  // Channel 2B - SCI7                     
#define XGCHID_PITCH7      0x2C  // Channel 2C - Periodic Interrupt Timer 7          
#define XGCHID_PITCH6      0x2D  // Channel 2D - Periodic Interrupt Timer 6          
#define XGCHID_PITCH5      0x2E  // Channel 2E - Periodic Interrupt Timer 5          
#define XGCHID_PITCH4      0x2F  // Channel 2F - Periodic Interrupt Timer 4          
//#define XGCHID_            0x30  // Channel 30 - Reserved                         
//#define XGCHID_            0x31  // Channel 31 - Reserved                         
#define XGCHID_SWI7        0x32  // Channel 32 - XGATE Software Trigger 7           
#define XGCHID_SWI6        0x33  // Channel 33 - XGATE Software Trigger 6           
#define XGCHID_SWI5        0x34  // Channel 34 - XGATE Software Trigger 5           
#define XGCHID_SWI4        0x35  // Channel 35 - XGATE Software Trigger 4           
#define XGCHID_SWI3        0x36  // Channel 36 - XGATE Software Trigger 3           
#define XGCHID_SWI2        0x37  // Channel 37 - XGATE Software Trigger 2           
#define XGCHID_SWI1        0x38  // Channel 38 - XGATE Software Trigger 1           
#define XGCHID_SWI0        0x39  // Channel 39 - XGATE Software Trigger 0           
#define XGCHID_PITCH3      0x3A  // Channel 3A - Periodic Interrupt Timer 3          
#define XGCHID_PITCH2      0x3B  // Channel 3B - Periodic Interrupt Timer 2          
#define XGCHID_PITCH1      0x3C  // Channel 3C - Periodic Interrupt Timer 1          
#define XGCHID_PITCH0      0x3D  // Channel 3D - Periodic Interrupt Timer 0          
//#define XGCHID_          0x3E  // Channel 3E - Reserved                         
#define XGCHID_API         0x3F  // Channel 3F - Autonomous Periodical interrupt API
#define XGCHID_LVI         0x40  // Channel 40 - Low Voltage interrupt LVI
#define XGCHID_IIC1        0x41  // Channel 41 - IIC1 Bus                 
#define XGCHID_SCI5        0x42  // Channel 42 - SCI5                     
#define XGCHID_SCI4        0x43  // Channel 43 - SCI4                     
#define XGCHID_SCI3        0x44  // Channel 44 - SCI3                     
#define XGCHID_SCI2        0x45  // Channel 45 - SCI2                     
#define XGCHID_PWMES       0x46  // Channel 46 - PWM Emergency Shutdown   
#define XGCHID_PTP         0x47  // Channel 47 - Port P Interrupt         
#define XGCHID_CAN4TX      0x48  // Channel 48 - CAN4 transmit            
#define XGCHID_CAN4RX      0x49  // Channel 49 - CAN4 receive             
#define XGCHID_CAN4ERR     0x4A  // Channel 4A - CAN4 errors              
#define XGCHID_CAN4WUP     0x4B  // Channel 4B - CAN4 wake-up             
#define XGCHID_CAN3TX      0x4C  // Channel 4C - CAN3 transmit            
#define XGCHID_CAN3RX      0x4D  // Channel 4D - CAN3 receive             
#define XGCHID_CAN3ERR     0x4E  // Channel 4E - CAN3 errors              
#define XGCHID_CAN3WUP     0x4F  // Channel 4F - CAN3 wake-up             
#define XGCHID_CAN2TX      0x50  // Channel 50 - CAN2 transmit
#define XGCHID_CAN2RX      0x51  // Channel 51 - CAN2 receive 
#define XGCHID_CAN2ERR     0x52  // Channel 52 - CAN2 errors  
#define XGCHID_CAN2WUP     0x53  // Channel 53 - CAN2 wake-up 
#define XGCHID_CAN1TX      0x54  // Channel 54 - CAN1 transmit
#define XGCHID_CAN1RX      0x55  // Channel 55 - CAN1 receive 
#define XGCHID_CAN1ERR     0x56  // Channel 56 - CAN1 errors  
#define XGCHID_CAN1WUP     0x57  // Channel 57 - CAN1 wake-up 
#define XGCHID_CAN0TX      0x58  // Channel 58 - CAN0 transmit
#define XGCHID_CAN0RX      0x59  // Channel 59 - CAN0 receive 
#define XGCHID_CAN0ERR     0x5A  // Channel 5A - CAN0 errors  
#define XGCHID_CAN0WUP     0x5B  // Channel 5B - CAN0 wake-up 
#define XGCHID_FLASH       0x5C  // Channel 5C - FLASH 
#define XGCHID_FLASH_FAULT 0x5D  // Channel 5D - FLASH fault detect
#define XGCHID_SPI2        0x5E  // Channel 5E - SPI2  
#define XGCHID_SPI1        0x5F  // Channel 5F - SPI1
#define XGCHID_IIC0        0x60  // Channel 60 - IIC0 Bus                         
#define XGCHID_SCI6        0x61  // Channel 61 - SCI6                         
#define XGCHID_SCM         0x62  // Channel 62 - CRG Self Clock Mode              
#define XGCHID_PLLLOCK     0x63  // Channel 63 - CRG PLL lock                     
#define XGCHID_PACBOF      0x64  // Channel 64 - Pulse Accumulator B Overflow     
#define XGCHID_MODUF       0x65  // Channel 65 - Modulus Down Counter underflow   
#define XGCHID_PTH         0x66  // Channel 66 - Port H                           
#define XGCHID_PTJ         0x67  // Channel 67 - Port J