s12vregl_3v3v1.h

freescale 协处理器应用相关实例

/******************************************************************************
                                             COPYRIGHT (c) FREESCALE 2005  
                                                                           
File Name          :    $RCSfile: S12VREGL_3V3V1.h,v $                     
                                                                          
Current Revision :      $Revision: 1.0 $                                  
                                                                           
PURPOSE: header file for S12X VREGL register block                         
                                                                           
DESCRIPTION:  Defines the VREGL register block as a datastructure of       
              type tVREG.                                                 
                                                                           
UPDATE HISTORY                                                            
REV  AUTHOR      DATE        DESCRIPTION OF CHANGE                        
---  ------      --------    ---------------------                        
1.0  r54430      19/04/04    - Initial Revision                           


      *****************************************************************
      *File created by: Freescale East Kilbride MCD Applications Group*
      *****************************************************************

                                                                          
******************************************************************************/
/*===========================================================================*/
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/*****************************************************************************/

#ifndef S12VREGL_3V3V1_H       /*prevent duplicated includes */
#define S12VREGL_3V3V1_H

#include "S12_COMMON.h"

typedef union uVREGHTCL /* ----- factory use only */
{
  tU08   byte;
  struct
  {
    tU08 htif  :1;
    tU08 htie  :1;
    tU08 htds  :1;
    tU08       :1;
    tU08 vae   :1;
    tU08 vsel  :1;
    tU08 ttst  :1;
    tU08       :1;
  }bit;
} tVREGHTCL;

/*bit masks for VREGHTCL*/
#define HTIF   0x01  
#define HTIE   0x02
#define HTDS   0x04
#define VAE    0x10   
#define VSEL   0x20
#define TTST   0x40

typedef union uVREGCTRL
{
  tU08   byte;
  struct
  {
    tU08 lvif  :1;        /* low voltage interrupt flag */
    tU08 lvie  :1;        /* low voltage interrupt enable */
    tU08 lvds  :1;        /* low voltage detect status */
	 tU08 		:5;        /* not used */           
  }bit;
} tVREGCTRL;

/*bit masks for VREGCTRL*/
#define LVIF   0x01  
#define LVIE   0x02
#define LVDS   0x04

typedef union uVREGAPICL
{
  tU08   byte;
  struct
  {
    tU08 apif   :1;		  /* API interrupt flag */
    tU08 apie   :1;		  /* API interrupt enable */
    tU08 apife  :1;		  /* API module enable */
    tU08        :4;
    tU08 apiclk :1;
  } bit;
} tVREGAPICL;

/*bit masks for VREGAPICL*/
#define APIF   0x01  
#define APIE   0x02
#define APIFE  0x04
#define APICLK 0x80


typedef union uVREGAPITR
{
  tU08   byte;
  struct
  {
    tU08 rcexa  :1; /* ----- factory use only */
    tU08        :1;		  /* not used */
    tU08 apitr  :6;		  /* API trim bits */
  } bit;
} tVREGAPITR;

/*bit masks for VREGAPITR*/
#define RCEXA   0x01 /* ---- factory use only */
#define APTR0   0x04  
#define APTR1   0x08
#define APTR2   0x10
#define APTR3   0x20
#define APTR4   0x40
#define APTR5   0x80

typedef struct {           /* vreg datastructure   */
  volatile tVREGHTCL   vreghtcl;   /* factory use only */  
  volatile tVREGCTRL   vregctrl;   /* Vreg Control Register */ 
  volatile tVREGAPICL  vregapicl;  /* API Control Register */  
  volatile tVREGAPITR  vregapitr;  /* API trim Register */  
  volatile tU16        vregapir;   /* API rate Register - writeable only when API disabled */
  volatile tREG08      rsv6;     
  volatile tREG08      rsv7;     
} tVREG;

#endif /*S12VREGL_3V3V1_H */