xgate_vectors.cxgate

freescale 协处理器应用相关实例

interrupt void _XG_VEC_6B();  // Channel 6B - SCI0                             
interrupt void _XG_VEC_6C();  // Channel 6C - SPI0                             
interrupt void _XG_VEC_6D();  // Channel 6D - ECT Pulse accumulator input edge     
interrupt void _XG_VEC_6E();  // Channel 6E - ECT Pulse accumulator A overflow     
interrupt void _XG_VEC_6F();  // Channel 6F - Enhanced Capture Timer overflow  
interrupt void _XG_VEC_70();  // Channel 70 - Enhanced Capture Timer channel 7                                 
interrupt void _XG_VEC_71();  // Channel 71 - Enhanced Capture Timer channel 6 
interrupt void _XG_VEC_72();  // Channel 72 - Enhanced Capture Timer channel 5 
interrupt void _XG_VEC_73();  // Channel 73 - Enhanced Capture Timer channel 4 
interrupt void _XG_VEC_74();  // Channel 74 - Enhanced Capture Timer channel 3 
interrupt void _XG_VEC_75();  // Channel 75 - Enhanced Capture Timer channel 2 
interrupt void _XG_VEC_76();  // Channel 76 - Enhanced Capture Timer channel 1 
interrupt void _XG_VEC_77();  // Channel 77 - Enhanced Capture Timer channel 0 
interrupt void _XG_VEC_78();  // Channel 78 - Real Time Interrupt 

/************************* Functions *****************************************/
#pragma CODE_SEG XGATE_CODE

/******************************************************************************
Function Name	:	Default_XSR
Engineer		   :	r32151
Date			   :	02/03/05
Parameters		:	NONE
Returns			:	NONE
Notes			   :	error handler unused XGate vectors.
******************************************************************************/
void interrupt Default_XSR(void) {
  _asm("NOP");
  _asm("BRK");
}

/*****************************************************************************
XGATEVectorTable
XGATE vector table for S12XDE100
Each vector comprises two entries:
Program thread address, followed by thread variable pointer
This table must be copied to RAM, starting at the address contained in the
XGATE Vector Base Address Register (XGVBR) + XV_TABLE_OFFSET.  
This offset is required as not all of the XGATE vectors are used / declared.
On the 9S12XDE100 the first 30 vectors are not used: 
1Eh = 30; * 4bytes = 120 = 78h.
XVEC_TABLE_OFFSET is defined in xgate_vectors.h
*****************************************************************************/
const xgate_vector XgateVectorTable[] = {
                          // Channel # = Vector address / 2
  {_XG_VEC_1E, _XG_PRM_1E},  // Channel 1E - ATD1 compare                            
  {_XG_VEC_1F, _XG_PRM_1F},  // Channel 1F - ATD0 compare                            
  {_XG_VEC_20, _XG_PRM_20},  // Channel 20 - TIM Pulse accumulator input edge     
  {_XG_VEC_21, _XG_PRM_21},  // Channel 21 - TIM Pulse accumulator A overflow     
  {_XG_VEC_22, _XG_PRM_22},  // Channel 22 - TIM overflow  
  {_XG_VEC_23, _XG_PRM_23},  // Channel 23 - TIM channel 7                                 
  {_XG_VEC_24, _XG_PRM_24},  // Channel 24 - TIM channel 6 
  {_XG_VEC_25, _XG_PRM_25},  // Channel 25 - TIM channel 5 
  {_XG_VEC_26, _XG_PRM_26},  // Channel 26 - TIM channel 4 
  {_XG_VEC_27, _XG_PRM_27},  // Channel 27 - TIM channel 3 
  {_XG_VEC_28, _XG_PRM_28},  // Channel 28 - TIM channel 2 
  {_XG_VEC_29, _XG_PRM_29},  // Channel 29 - TIM channel 1 
  {_XG_VEC_2A, _XG_PRM_2A},  // Channel 2A - TIM channel 0 
  {_XG_VEC_2B, _XG_PRM_2B},  // Channel 2B - SCI7                     
  {_XG_VEC_2C, _XG_PRM_2C},  // Channel 2C - Periodic Interrupt Timer 7          
  {_XG_VEC_2D, _XG_PRM_2D},  // Channel 2D - Periodic Interrupt Timer 6          
  {_XG_VEC_2E, _XG_PRM_2E},  // Channel 2E - Periodic Interrupt Timer 5          
  {_XG_VEC_2F, _XG_PRM_2F},  // Channel 2F - Periodic Interrupt Timer 4          
  {_XG_VEC_30, _XG_PRM_30},  // Channel 30 - Reserved
  {_XG_VEC_31, _XG_PRM_31},  // Channel 31 - Reserved     
  {_XG_VEC_32, _XG_PRM_32},  // Channel 32 - XGATE Software Trigger 7           
  {_XG_VEC_33, _XG_PRM_33},  // Channel 33 - XGATE Software Trigger 6           
  {_XG_VEC_34, _XG_PRM_34},  // Channel 34 - XGATE Software Trigger 5           
  {_XG_VEC_35, _XG_PRM_35},  // Channel 35 - XGATE Software Trigger 4           
  {_XG_VEC_36, _XG_PRM_36},  // Channel 36 - XGATE Software Trigger 3           
  {_XG_VEC_37, _XG_PRM_37},  // Channel 37 - XGATE Software Trigger 2           
  {_XG_VEC_38, _XG_PRM_38},  // Channel 38 - XGATE Software Trigger 1           
  {_XG_VEC_39, _XG_PRM_39},  // Channel 39 - XGATE Software Trigger 0           
  {_XG_VEC_3A, _XG_PRM_3A},  // Channel 3A - Periodic Interrupt Timer 3          
  {_XG_VEC_3B, _XG_PRM_3B},  // Channel 3B - Periodic Interrupt Timer 2          
  {_XG_VEC_3C, _XG_PRM_3C},  // Channel 3C - Periodic Interrupt Timer 1          
  {_XG_VEC_3D, _XG_PRM_3D},  // Channel 3D - Periodic Interrupt Timer 0          
  {_XG_VEC_3E, _XG_PRM_3E},  // Channel 3E - Reserved                           
  {_XG_VEC_3F, _XG_PRM_3F},  // Channel 3F - Autonomous Periodical interrupt API
  {_XG_VEC_40, _XG_PRM_40},  // Channel 40 - Low Voltage interrupt LVI
  {_XG_VEC_41, _XG_PRM_41},  // Channel 41 - IIC1 Bus                 
  {_XG_VEC_42, _XG_PRM_42},  // Channel 42 - SCI5                     
  {_XG_VEC_43, _XG_PRM_43},  // Channel 43 - SCI4                     
  {_XG_VEC_44, _XG_PRM_44},  // Channel 44 - SCI3                     
  {_XG_VEC_45, _XG_PRM_45},  // Channel 45 - SCI2                     
  {_XG_VEC_46, _XG_PRM_46},  // Channel 46 - PWM Emergency Shutdown   
  {_XG_VEC_47, _XG_PRM_47},  // Channel 47 - Port P Interrupt         
  {_XG_VEC_48, _XG_PRM_48},  // Channel 48 - CAN4 transmit            
  {_XG_VEC_49, _XG_PRM_49},  // Channel 49 - CAN4 receive             
  {_XG_VEC_4A, _XG_PRM_4A},  // Channel 4A - CAN4 errors              
  {_XG_VEC_4B, _XG_PRM_4B},  // Channel 4B - CAN4 wake-up             
  {_XG_VEC_4C, _XG_PRM_4C},  // Channel 4C - CAN3 transmit            
  {_XG_VEC_4D, _XG_PRM_4D},  // Channel 4D - CAN3 receive             
  {_XG_VEC_4E, _XG_PRM_4E},  // Channel 4E - CAN3 errors              
  {_XG_VEC_4F, _XG_PRM_4F},  // Channel 4F - CAN3 wake-up             
  {_XG_VEC_50, _XG_PRM_50},  // Channel 50 - CAN2 transmit
  {_XG_VEC_51, _XG_PRM_51},  // Channel 51 - CAN2 receive 
  {_XG_VEC_52, _XG_PRM_52},  // Channel 52 - CAN2 errors  
  {_XG_VEC_53, _XG_PRM_53},  // Channel 53 - CAN2 wake-up 
  {_XG_VEC_54, _XG_PRM_54},  // Channel 54 - CAN1 transmit
  {_XG_VEC_55, _XG_PRM_55},  // Channel 55 - CAN1 receive 
  {_XG_VEC_56, _XG_PRM_56},  // Channel 56 - CAN1 errors  
  {_XG_VEC_57, _XG_PRM_57},  // Channel 57 - CAN1 wake-up 
  {_XG_VEC_58, _XG_PRM_58},  // Channel 58 - CAN0 transmit
  {_XG_VEC_59, _XG_PRM_59},  // Channel 59 - CAN0 receive 
  {_XG_VEC_5A, _XG_PRM_5A},  // Channel 5A - CAN0 errors  
  {_XG_VEC_5B, _XG_PRM_5B},  // Channel 5B - CAN0 wake-up 
  {_XG_VEC_5C, _XG_PRM_5C},  // Channel 5C - FLASH 
  {_XG_VEC_5D, _XG_PRM_5D},  // Channel 5D - FLASH fault detect
  {_XG_VEC_5E, _XG_PRM_5E},  // Channel 5E - SPI2  
  {_XG_VEC_5F, _XG_PRM_5F},  // Channel 5F - SPI1
  {_XG_VEC_60, _XG_PRM_60},  // Channel 60 - IIC0 Bus                         
  {_XG_VEC_61, _XG_PRM_61},  // Channel 61 - SCI6                         
  {_XG_VEC_62, _XG_PRM_62},  // Channel 62 - CRG Self Clock Mode              
  {_XG_VEC_63, _XG_PRM_63},  // Channel 63 - CRG PLL lock                     
  {_XG_VEC_64, _XG_PRM_64},  // Channel 64 - Pulse Accumulator B Overflow     
  {_XG_VEC_65, _XG_PRM_65},  // Channel 65 - Modulus Down Counter underflow   
  {_XG_VEC_66, _XG_PRM_66},  // Channel 66 - Port H                           
  {_XG_VEC_67, _XG_PRM_67},  // Channel 67 - Port J                           
  {_XG_VEC_68, _XG_PRM_68},  // Channel 68 - ATD1                             
  {_XG_VEC_69, _XG_PRM_69},  // Channel 69 - ATD0                             
  {_XG_VEC_6A, _XG_PRM_6A},  // Channel 6A - SCI1                             
  {_XG_VEC_6B, _XG_PRM_6B},  // Channel 6B - SCI0                             
  {_XG_VEC_6C, _XG_PRM_6C},  // Channel 6C - SPI0                             
  {_XG_VEC_6D, _XG_PRM_6D},  // Channel 6D - ECT Pulse accumulator input edge     
  {_XG_VEC_6E, _XG_PRM_6E},  // Channel 6E - ECT Pulse accumulator A overflow     
  {_XG_VEC_6F, _XG_PRM_6F},  // Channel 6F - Enhanced Capture Timer overflow  
  {_XG_VEC_70, _XG_PRM_70},  // Channel 70 - Enhanced Capture Timer channel 7                                 
  {_XG_VEC_71, _XG_PRM_71},  // Channel 71 - Enhanced Capture Timer channel 6 
  {_XG_VEC_72, _XG_PRM_72},  // Channel 72 - Enhanced Capture Timer channel 5 
  {_XG_VEC_73, _XG_PRM_73},  // Channel 73 - Enhanced Capture Timer channel 4 
  {_XG_VEC_74, _XG_PRM_74},  // Channel 74 - Enhanced Capture Timer channel 3 
  {_XG_VEC_75, _XG_PRM_75},  // Channel 75 - Enhanced Capture Timer channel 2 
  {_XG_VEC_76, _XG_PRM_76},  // Channel 76 - Enhanced Capture Timer channel 1 
  {_XG_VEC_77, _XG_PRM_77},  // Channel 77 - Enhanced Capture Timer channel 0 
  {_XG_VEC_78, _XG_PRM_78}   // Channel 78 - Real Time Interrupt 
};