interrupts.h

freescale 协处理器应用相关实例

      /* Interrupt priority      */
   #define _INT_PRI_BE                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_BE                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_BE                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5F                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5F                   (xgdataptr)0x5F  

/* SPI2 :: CPU Vector 0xFFBC :: XGate Channel 5E *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_BC                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_BC                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_BC                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5E                   (xgdataptr)0x5E  

/*** TIM - Standard Timer ***/
/* Standard Timer channel 0 :: CPU Vector 0xFF54 :: XGate Channel 2A */
      /* Interrupt priority      */
   #define _INT_PRI_54                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_54                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_54                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2A                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2A                   (xgdataptr)0x2A  

/* Standard Timer channel 1 :: CPU Vector 0xFF52 :: XGate Channel 29 */
      /* Interrupt priority      */
   #define _INT_PRI_52                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_52                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_52                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_29                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_29                   (xgdataptr)0x29  

/* Standard Timer channel 2 :: CPU Vector 0xFF50 :: XGate Channel 28 */
      /* Interrupt priority      */ 
   #define _INT_PRI_50                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_50                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_50                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_28                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_28                   (xgdataptr)0x28  

/* Standard Timer channel 3 :: CPU Vector 0xFF4E :: XGate Channel 27 */
      /* Interrupt priority      */
   #define _INT_PRI_4E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_4E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_4E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_27                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_27                   (xgdataptr)0x27  

/* Standard Timer channel 4 :: CPU Vector 0xFF4C :: XGate Channel 26 */
      /* Interrupt priority      */
   #define _INT_PRI_4C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_4C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_4C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_26                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_26                   (xgdataptr)0x26  

/* Standard Timer channel 5 :: CPU Vector 0xFF4A :: XGate Channel 25 */
      /* Interrupt priority      */
   #define _INT_PRI_4A                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_4A                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_4A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_25                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_25                   (xgdataptr)0x25  

/* Standard Timer channel 6 :: CPU Vector 0xFF48 :: XGate Channel 24 */
      /* Interrupt priority      */
   #define _INT_PRI_48                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_48                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_48                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_24                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_24                   (xgdataptr)0x24  

/* Standard Timer channel 7 :: CPU Vector 0xFF46 :: XGate Channel 23 */
      /* Interrupt priority      */
   #define _INT_PRI_46                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_46                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_46                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_23                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_23                   (xgdataptr)0x23  

/* Standard Timer Overflow :: CPU Vector 0xFF44 :: XGate Channel 22 **/
      /* Interrupt priority      */
   #define _INT_PRI_44                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_44                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_44                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_22                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_22                   (xgdataptr)0x22  

/* Pulse accumulator A overflow  :: CPU Vector 0xFF42 :: XGate Channel 21 ****/
      /* Interrupt priority      */
   #define _INT_PRI_42                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_42                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_42                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_21                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_21                   (xgdataptr)0x21  

/* Pulse accumulator input edge :: CPU Vector 0xFF40 :: XGate Channel 20 *****/
      /* Interrupt priority      */
   #define _INT_PRI_40                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_40                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_40                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_20                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_20                   (xgdataptr)0x20  

/*** VREG ***/
/* API Autonomous Periodical Interrupt :: CPU Vector 0xFF7E :: XGate Channel 3F */
      /* Interrupt priority      */
   #define _INT_PRI_7E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_7E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_7E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3F                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3F                   (xgdataptr)0x3F  

/* LVI Low Voltage Interrupt :: CPU Vector 0xFF80 :: XGate Channel 40 ********/
      /* Interrupt priority      */
   #define _INT_PRI_80                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_80                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_80                  LVI_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_40                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_40                   (xgdataptr)0x40  

/*** XGATE ***/
/* XGATE Software Trigger 0 :: CPU Vector 0xFF72 :: XGate Channel 39 *********/
      /* Interrupt priority      */
   #define _INT_PRI_72                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_72                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_72                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_39                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_39                   (xgdataptr)0x39  

/* XGATE Software Trigger 1 :: CPU Vector 0xFF70 :: XGate Channel 38 *********/
      /* Interrupt priority      */
   #define _INT_PRI_70                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_70                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_70                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_38                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_38                   (xgdataptr)0x38  

/* XGATE Software Trigger 2 :: CPU Vector 0xFF6E :: XGate Channel 37 *********/
      /* Interrupt priority      */
   #define _INT_PRI_6E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_6E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_6E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_37                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_37                   (xgdataptr)0x37  

/* XGATE Software Trigger 3 :: CPU Vector 0xFF6C :: XGate Channel 36 *********/
      /* Interrupt priority      */
   #define _INT_PRI_6C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_6C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_6C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_36                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_36                   (xgdataptr)0x36  

/* XGATE Software Trigger 4 :: CPU Vector 0xFF6A :: XGate Channel 35 *********/
      /* Interrupt priority      */
   #define _INT_PRI_6A                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_6A                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_6A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_35                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_35                   (xgdataptr)0x35  

/* XGATE Software Trigger 5 :: CPU Vector 0xFF68 :: XGate Channel 34 *********/
      /* Interrupt priority      */
   #define _INT_PRI_68                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_68                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_68                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_34                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_34                   (xgdataptr)0x34  

/* XGATE Software Trigger 6 :: CPU Vector 0xFF66 :: XGate Channel 33 *********/
      /* Interrupt priority      */
   #define _INT_PRI_66                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_66                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_66                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_33                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_33                   (xgdataptr)0x33  

/* XGATE Software Trigger 7 :: CPU Vector 0xFF64 :: XGate Channel 32 *********/
      /* Interrupt priority      */
   #define _INT_PRI_64                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_64                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_64                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_32                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_32                   (xgdataptr)0x32  


/*** RESERVED ***/
/* Reserved :: CPU Vector 0xFF7C :: XGate Channel 3E *************************/
      /* Interrupt priority      */
   #define _INT_PRI_7C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_7C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_7C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3E                   (xgdataptr)0x3E
    
/* Reserved :: CPU vector 0xFF60 :: XGate Channel 30 *************************/
   /* Interrupt priority      */
   #define _INT_PRI_60                  LEVEL1                
   /* Interrupt Service Owner */
   #define _INT_SER_60                  CPU_REQUEST           
   /* CPU Service Vector      */
   #define _S12_VEC_60                  Default_ISR        
   /* XGate Service Vector    */
   #define _XG_VEC_30                   Default_XSR             
   /* XGate Service Parameter */
   #define _XG_PRM_30                   (xgdataptr)0x30

/* Reserved :: CPU Vector 0xFF62 :: XGate Channel 31 *************************/
      /* Interrupt priority      */
   #define _INT_PRI_62                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_62                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_62                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_31                   Default_XSR       
      /* XGate Service Parameter */
   #define _XG_PRM_31                   (xgdataptr)0x31  


#endif /* INTERRUPTS_H */