interrupts.h

freescale 协处理器应用相关实例

   #define _XG_PRM_4F                   (xgdataptr)0x4F  

/* 0x90 MSCAN 4 transmit :: CPU Vector 0xFF90 :: XGate Channel 48 ************/
      /* Interrupt priority      */
   #define _INT_PRI_90                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_90                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_90                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_48                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_48                   (xgdataptr)0x48  

/* MSCAN 4 receive :: CPU Vector 0xFF92 :: XGate Channel 49 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_92                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_92                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_92                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_49                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_49                   (xgdataptr)0x49  

/* MSCAN 4 errors :: CPU Vector 0xFF94 :: XGate Channel 4A *******************/
      /* Interrupt priority      */
   #define _INT_PRI_94                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_94                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_94                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4A                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_4A                   (xgdataptr)0x4A  

/* MSCAN 4 wake-up  :: CPU Vector 0xFF96 :: XGate Channel 4B *****************/
      /* Interrupt priority      */
   #define _INT_PRI_96                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_96                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_96                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4B                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_4B                   (xgdataptr)0x4B  

/*** PIM Key Wakeup Ports ***/
/* Port H :: CPU Vector 0xFFCC :: XGate Channel 66 ***************************/
      /* Interrupt priority      */
   #define _INT_PRI_CC                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_CC                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_CC                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_66                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_66                   (xgdataptr)0x66  

/* Port J :: CPU Vector 0xFFCE :: XGate Channel 67 ***************************/
      /* Interrupt priority      */
   #define _INT_PRI_CE                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_CE                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_CE                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_67                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_67                   (xgdataptr)0x67  

/* Port P Interrupt :: CPU Vector 0xFF8E :: XGate Channel 47 *****************/
      /* Interrupt priority      */
   #define _INT_PRI_8E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_8E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_8E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_47                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_47                   (xgdataptr)0x47  

/*** PIT ***/
/* Periodic Interrupt Timer 0 :: CPU Vector 0xFF7A :: XGate Channel 3D *******/
      /* Interrupt priority      */
   #define _INT_PRI_7A                  LEVEL3                
      /* Interrupt Service Owner */
   #define _INT_SER_7A                  XGATE_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_7A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3D                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3D                   (xgdataptr)0x3D  

/* Periodic Interrupt Timer 1 :: CPU Vector 0xFF78 :: XGate Channel 3C *******/
      /* Interrupt priority      */
   #define _INT_PRI_78                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_78                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_78                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3C                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3C                   (xgdataptr)0x3C  

/* Periodic Interrupt Timer 2 :: CPU Vector 0xFF76 :: XGate Channel 3B *******/
      /* Interrupt priority      */
   #define _INT_PRI_76                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_76                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_76                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3B                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3B                   (xgdataptr)0x3B  

/* Periodic Interrupt Timer 3 :: CPU Vector 0xFF74 :: XGate Channel 3A *******/
      /* Interrupt priority      */
   #define _INT_PRI_74                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_74                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_74                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_3A                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_3A                   (xgdataptr)0x3A  

/* Periodic Interrupt Timer 4 :: CPU Vector 0xFF5E :: XGate Channel 2F *******/
      /* Interrupt priority      */
   #define _INT_PRI_5E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_5E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_5E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2F                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2F                   (xgdataptr)0x2F  

/* Periodic Interrupt Timer 5 :: CPU Vector 0xFF5C :: XGate Channel 2E *******/
      /* Interrupt priority      */
   #define _INT_PRI_5C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_5C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_5C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2E                   (xgdataptr)0x2E  

/* Periodic Interrupt Timer 6 :: CPU Vector 0xFF5A :: XGate Channel 2D *******/
      /* Interrupt priority      */
   #define _INT_PRI_5A                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_5A                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_5A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2D                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2D                   (xgdataptr)0x2D  

/* Periodic Interrupt Timer 7 :: CPU Vector 0xFF58 :: XGate Channel 2C *******/
      /* Interrupt priority      */
   #define _INT_PRI_58                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_58                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_58                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2C                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2C                   (xgdataptr)0x2C  


/*** PWM ***/
/* PWM Emergency Shutdown :: CPU Vector 0xFF8C :: XGate Channel 46 ***********/
      /* Interrupt priority      */
   #define _INT_PRI_8C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_8C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_8C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_46                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_46                   (xgdataptr)0x46  

/*** RTI ***/
/* Real Time Interrupt :: CPU Vector 0xFFF0 :: XGate Channel 78 **************/
      /* Interrupt priority      */
   #define _INT_PRI_F0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_F0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_F0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_78                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_78                   (xgdataptr)0x78  

/*** SCI ***/
/* SCI0 :: CPU Vector 0xFFD6 :: XGate Channel 6B *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_D6                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_D6                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_D6                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6B                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6B                   (xgdataptr)0x6B  

/* SCI1 :: CPU Vector 0xFFD4 :: XGate Channel 6A *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_D4                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_D4                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_D4                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6A                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6A                   (xgdataptr)0x6A  

/* SCI2 :: CPU Vector 0xFF8A :: XGate Channel 45 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_8A                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_8A                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_8A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_45                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_45                   (xgdataptr)0x45  

/* SCI3 :: CPU Vector 0xFF88 :: XGate Channel 44 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_88                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_88                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_88                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_44                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_44                   (xgdataptr)0x44  

/* SCI4 :: CPU Vector 0xFF86 :: XGate Channel 43 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_86                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_86                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_86                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_43                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_43                   (xgdataptr)0x43  

/* SCI5 :: CPU Vector 0xFF84 :: XGate Channel 42 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_84                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_84                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_84                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_42                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_42                   (xgdataptr)0x42  

/* SCI6 :: CPU Vector 0xFFC2 :: XGate Channel 61 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_C2                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_C2                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_C2                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_61                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_61                   (xgdataptr)0x61  

/* SCI7 :: CPU Vector 0xFF56 :: XGate Channel 2B *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_56                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_56                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_56                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_2B                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_2B                   (xgdataptr)0x2B  

/*** SPI ***/
/* SPI0 :: CPU Vector 0xFFD8 :: XGate Channel 6C *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_D8                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_D8                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_D8                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6C                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6C                   (xgdataptr)0x6C  

/* SPI1 :: CPU Vector 0xFFBE :: XGate Channel 5F *****************************/