interrupts.h

freescale 协处理器应用相关实例

      /* Interrupt Service Owner */
   #define _INT_SER_E2                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_E2                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_71                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_71                   (xgdataptr)0x71  

/* Enhanced Capture Timer channel 7 :: CPU Vector 0xFFE0 :: XGate Channel 70 */
      /* Interrupt priority      */
   #define _INT_PRI_E0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_E0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_E0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_70                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_70                   (xgdataptr)0x70  

/* Enhanced Capture Timer Overflow :: CPU Vector 0xFFDE :: XGate Channel 6F **/
      /* Interrupt priority      */
   #define _INT_PRI_DE                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_DE                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_DE                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6F                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6F                   (xgdataptr)0x6F  

/* Modulus Down Counter Underflow :: CPU Vector 0xFFCA :: XGate Channel 65 ***/
      /* Interrupt priority      */
   #define _INT_PRI_CA                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_CA                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_CA                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_65                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_65                   (xgdataptr)0x65  

/* Pulse accumulator input edge :: CPU Vector 0xFFDA :: XGate Channel 6D *****/
      /* Interrupt priority      */
   #define _INT_PRI_DA                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_DA                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_DA                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6D                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6D                   (xgdataptr)0x6D  

/* Pulse accumulator A overflow  :: CPU Vector 0xFFDC :: XGate Channel 6E ****/
      /* Interrupt priority      */
   #define _INT_PRI_DC                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_DC                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_DC                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_6E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_6E                   (xgdataptr)0x6E  

/* Pulse accumulator B overflow :: CPU Vector 0xFFC8 :: XGate Channel 64 *****/
      /* Interrupt priority      */
   #define _INT_PRI_C8                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_C8                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_C8                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_64                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_64                   (xgdataptr)0x64  

/*** FLASH and EEEPROM ***/
/* Flash :: CPU Vector 0xFFB8 :: XGate Channel 5C ****************************/
      /* Interrupt priority      */
   #define _INT_PRI_B8                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_B8                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_B8                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5C                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5C                   (xgdataptr)0x5C  

/* Flash error detect :: CPU Vector 0xFFBA :: XGate Channel 5D ***************/
      /* Interrupt priority      */
   #define _INT_PRI_BA                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_BA                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_BA                  FTM_ERROR_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5D                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5D                   (xgdataptr)0x5D  

/*** IIC ***/
/* IIC0 :: CPU Vector 0xFFC0 :: XGate Channel 60 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_C0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_C0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_C0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_60                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_60                   (xgdataptr)0x60  

/* IIC1 :: CPU Vector 0xFF82 :: XGate Channel 41 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_82                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_82                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_82                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_41                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_41                   (xgdataptr)0x41  

/*** MSCAN ***/
/* MSCAN 0 transmit :: CPU Vector 0xFFB0 :: XGate Channel 58 *****************/
      /* Interrupt priority      */
   #define _INT_PRI_B0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_B0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_B0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_58                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_58                   (xgdataptr)0x58  

/* MSCAN 0 receive :: CPU Vector 0xFFB2 :: XGate Channel 59 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_B2                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_B2                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_B2                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_59                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_59                   (xgdataptr)0x59  

/* MSCAN 0 errors :: CPU Vector 0xFFB4 :: XGate Channel 5A *******************/
      /* Interrupt priority      */
   #define _INT_PRI_B4                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_B4                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_B4                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5A                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5A                   (xgdataptr)0x5A  

/* MSCAN 0 wake-up :: CPU Vector 0xFFB6 :: XGate Channel 5B ******************/
      /* Interrupt priority      */
   #define _INT_PRI_B6                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_B6                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_B6                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_5B                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_5B                   (xgdataptr)0x5B  

/* MSCAN 1 transmit :: CPU Vector 0xFFA8 :: XGate Channel 54 *****************/
      /* Interrupt priority      */
   #define _INT_PRI_A8                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_A8                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_A8                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_54                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_54                   (xgdataptr)0x54  

/* MSCAN 1 receive :: CPU Vector 0xFFAA :: XGate Channel 55 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_AA                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_AA                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_AA                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_55                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_55                   (xgdataptr)0x55  

/* MSCAN 1 errors :: CPU Vector 0xFFAC :: XGate Channel 56 *******************/
      /* Interrupt priority      */
   #define _INT_PRI_AC                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_AC                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_AC                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_56                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_56                   (xgdataptr)0x56  

/* MSCAN 1 wake-up :: CPU Vector 0xFFAE :: XGate Channel 57 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_AE                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_AE                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_AE                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_57                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_57                   (xgdataptr)0x57  

/* MSCAN 2 transmit :: CPU Vector 0xFFA0 :: XGate Channel 50 *****************/
      /* Interrupt priority      */
   #define _INT_PRI_A0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_A0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_A0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_50                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_50                   (xgdataptr)0x50  

/* MSCAN 2 receive :: CPU Vector 0xFFA2 :: XGate Channel 51 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_A2                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_A2                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_A2                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_51                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_51                   (xgdataptr)0x51  

/* MSCAN 2 errors  :: CPU Vector 0xFFA4 :: XGate Channel 52 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_A4                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_A4                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_A4                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_52                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_52                   (xgdataptr)0x52  

/* MSCAN 2 wake-up :: CPU Vector 0xFFA6 :: XGate Channel 53 ******************/
      /* Interrupt priority      */
   #define _INT_PRI_A6                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_A6                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_A6                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_53                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_53                   (xgdataptr)0x53  

/* MSCAN 3 transmit :: CPU Vector 0xFF98 :: XGate Channel 4C *****************/
      /* Interrupt priority      */
   #define _INT_PRI_98                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_98                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_98                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4C                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_4C                   (xgdataptr)0x4C  

/* MSCAN 3 receive :: CPU Vector 0xFF9A :: XGate Channel 4D ******************/
      /* Interrupt priority      */
   #define _INT_PRI_9A                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_9A                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_9A                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4D                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_4D                   (xgdataptr)0x4D  

/* MSCAN 3 errors :: CPU Vector 0xFF9C :: XGate Channel 4E *******************/
      /* Interrupt priority      */
   #define _INT_PRI_9C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_9C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_9C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_4E                   (xgdataptr)0x4E  

/* MSCAN 3 wake-up :: CPU Vector 0xFF9E :: XGate Channel 4F ******************/
      /* Interrupt priority      */
   #define _INT_PRI_9E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_9E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_9E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_4F                   Default_XSR            
      /* XGate Service Parameter */