interrupts.h

freescale 协处理器应用相关实例

/******************************************************************************
                                                   COPYRIGHT (c) Freescale 2005  
                                                                          
File Name          :    $RCSfile: interrupts.h,v $                     
                                                                          
Current Revision :      $Revision: 1.1 $                                  
                                                                          
PURPOSE: header file defining all interrupts behaviour on HCS12XEP100.                         
                                                                          
DESCRIPTION:  Defines interrupt priority, service target and service routines 
              for all interrupt vectors on HCS12XEP100 on a vector by vector
              basis.
              Controls the XGATE freeze and fake activity behaviour and the 
              size of the memory allocated for the two XGATE stack regions.
                 
                                                                          
UPDATE HISTORY                                                            
REV  AUTHOR      DATE        DESCRIPTION OF CHANGE                        
---  ------      --------    ---------------------                        
1.0  r32151      12/10/05    Initial Revision.   
1.1  r32151      26/01/06    Changed XGATE stack initalisation from actual
                             addresses to stack size values in order to 
                             facilitate changing the XGATE memory map 
                             without having to explictly manage changes to 
                             the stack locations.

     *******************************************************************
     * File created by: Freescale East Kilbride MCD Applications Group *
     *******************************************************************

                                                                          
******************************************************************************/
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#ifndef INTERRUPTS_H	/* prevent duplicated includes */
#define INTERRUPTS_H


/************************* configuration field settings **********************/
#define KEY0 0xFFFF
#define KEY1 0xFFFF
#define KEY2 0xFFFF
#define KEY3 0xFFFF


#define FOPT  0xFF
#define FPROT 0xFF
#define EPROT 0xFF
#define NVBYT 0xFF
#define FSEC  0xFE    /* don't change unless you want to secure!!!!! */

/************ copy any typedefs for XGate Parameters here *******************/





/************ copy extern declarations for XGate Parameters here ************/
#pragma DATA_SEG SHARED_DATA






/************ XGATE OPTIONS *************************************************/
/* XGate will be configured for :
   XGate enabled 
   Global enable for interrupts to CPU core enabled 
   Any pending interrupt flag cleared */

/*** Un/comment out either of these other options as required ***/
   #define XG_FREEZES        /* XGate freeze enabled  */
                             /* halts XGate activity in BDM active mode */					  

//   #define XG_FAKE_ACTIVITY  /* XGate fake activity enabled  */
                             /* With CPU stopped, clocks continue ouside */
                             /*  XGate thread */

/* XGate Priority Level - for all SIF XGate channel interrupt flags */ 
   #define _XGATE_PRI  						 LEVEL1

/**** XGATE Stack Initialisation ****/
   
   #define XGATE_LO_STACK_SIZE 0x40		/* words */
   #define XGATE_HI_STACK_SIZE 0x40		/* words */

/***************** interrupt settings ***************************************/

   #define CPU_VECTOR_BASE 0x3F /* 0x3F00 - 0x3FFF ; default is 0xFF, 0xFF00 - 0xFFFF*/


/************************* #defines ******************************************/
#define LEVEL0 PRIOLVL0
#define LEVEL1 PRIOLVL1 
#define LEVEL2 PRIOLVL2 
#define LEVEL3 PRIOLVL3 
#define LEVEL4 PRIOLVL4 
#define LEVEL5 PRIOLVL5 
#define LEVEL6 PRIOLVL6 
#define LEVEL7 PRIOLVL7 
#define XGATE_REQUEST RQST
#define CPU_REQUEST   0

/*** CPU ONLY ***/

/* Spurious  :: CPU Vector 0xFF10 :: NO XGate Channel  ***************************/
      /* CPU Service Vector      */
   #define _S12_VEC_10                  Spurious_ISR    

/* SYS :: CPU Vector 0xFF12 :: NO XGate Channel ******************************/
      /* CPU Service Vector      */
   #define _S12_VEC_12                  System_Call_ISR    

/* MPU Access error :: CPU Vector 0xFF14:: NO XGate Channel *****/
      /* CPU Service Vector      */
   #define _S12_VEC_14                  MPU_ISR    
  
/* XGATE error :: CPU Vector 0xFF16:: :: NO XGate Channel ****************/
      /* CPU Service Vector      */
   #define _S12_VEC_16                  XGATE_Error_ISR    

/* IRQ  :: CPU Vector 0xFFF2 :: NO XGate Channel *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_F2                  LEVEL1                
      /* CPU Service Vector      */
   #define _S12_VEC_F2                  Default_ISR    

/* XIRQ  :: CPU Vector 0xFFF4 :: NO XGate Channel  ***************************/
      /* CPU Service Vector      */
   #define _S12_VEC_F4                  XIRQ_ISR    

/* SWI :: CPU Vector 0xFFF6 :: NO XGate Channel ******************************/
      /* CPU Service Vector      */
   #define _S12_VEC_F6                  SWI_ISR    

/* Unallocated instruction trap :: CPU Vector 0xFFF8 :: NO XGate Channel *****/
      /* CPU Service Vector      */
   #define _S12_VEC_F8                  Trap_ISR    
  
/* COP failure reset :: CPU Vector 0xFFFA :: XGate Channel 3D ****************/
      /* CPU Service Vector      */
   #define _S12_VEC_FA                  COP_ISR    

/* Clock monitor fail reset :: CPU Vector 0xFFFC :: NO XGate Channel *********/
      /* CPU Service Vector      */
   #define _S12_VEC_FC                  CM_ISR    

/* Reset Vector :: CPU Vector 0xFFFE :: NO XGate Channel *********************/
      /* CPU Service Vector      */
   #define _S12_VEC_FE                  _Startup   



/*** ATD ***/
/* ATD0 :: CPU Vector 0xFFD2 :: XGate Channel 69 *****************************/
      /* Interrupt priority      */
   #define _INT_PRI_D2                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_D2                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_D2                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_69                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_69                   (xgdataptr)0x69  

/* ATD0 Compare :: CPU Vector 0xFF3E :: XGate Channel 1F ********************/
      /* Interrupt priority      */
   #define _INT_PRI_3E                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_3E                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_3E                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_1F                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_1F                   (xgdataptr)0x1F  

/* ATD1 :: CPU Vector 0xFFD0 :: XGate Channel 68 ****************************/
      /* Interrupt priority      */
   #define _INT_PRI_D0                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_D0                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_D0                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_68                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_68                   (xgdataptr)0x68  

/* ATD1 Compare :: CPU Vector 0xFF3C :: XGate Channel 1E ********************/
      /* Interrupt priority      */
   #define _INT_PRI_3C                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_3C                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_3C                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_1E                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_1E                   (xgdataptr)0x1E  

/*** CRG ***/
/* CRG Self Clock Mode :: CPU Vector 0xFFC4 :: XGate Channel 62 *************/
      /* Interrupt priority      */
   #define _INT_PRI_C4                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_C4                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_C4                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_62                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_62                   (xgdataptr)0x62  

/* CRG PLL lock :: CPU Vector 0xFFC6 :: XGate Channel 63 ********************/
      /* Interrupt priority      */
   #define _INT_PRI_C6                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_C6                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_C6                  CRG_PLL    
      /* XGate Service Vector    */
   #define _XG_VEC_63                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_63                   (xgdataptr)0x63  

/*** ECT ***/
/* Enhanced Capture Timer channel 0 :: CPU Vector 0xFFEE :: XGate Channel 77 */
      /* Interrupt priority      */
   #define _INT_PRI_EE                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_EE                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_EE                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_77                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_77                   (xgdataptr)0x77  

/* Enhanced Capture Timer channel 1 :: CPU Vector 0xFFEC :: XGate Channel 76 */
      /* Interrupt priority      */
   #define _INT_PRI_EC                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_EC                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_EC                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_76                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_76                   (xgdataptr)0x76  

/* Enhanced Capture Timer channel 2 :: CPU Vector 0xFFEA :: XGate Channel 75 */
      /* Interrupt priority      */ 
   #define _INT_PRI_EA                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_EA                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_EA                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_75                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_75                   (xgdataptr)0x75  

/* Enhanced Capture Timer channel 3 :: CPU Vector 0xFFE8 :: XGate Channel 74 */
      /* Interrupt priority      */
   #define _INT_PRI_E8                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_E8                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_E8                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_74                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_74                   (xgdataptr)0x74  

/* Enhanced Capture Timer channel 4 :: CPU Vector 0xFFE6 :: XGate Channel 73 */
      /* Interrupt priority      */
   #define _INT_PRI_E6                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_E6                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_E6                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_73                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_73                   (xgdataptr)0x73  

/* Enhanced Capture Timer channel 5 :: CPU Vector 0xFFE4 :: XGate Channel 72 */
      /* Interrupt priority      */
   #define _INT_PRI_E4                  LEVEL1                
      /* Interrupt Service Owner */
   #define _INT_SER_E4                  CPU_REQUEST           
      /* CPU Service Vector      */
   #define _S12_VEC_E4                  Default_ISR    
      /* XGate Service Vector    */
   #define _XG_VEC_72                   Default_XSR            
      /* XGate Service Parameter */
   #define _XG_PRM_72                   (xgdataptr)0x72  

/* Enhanced Capture Timer channel 6 :: CPU Vector 0xFFE2 :: XGate Channel 71 */
      /* Interrupt priority      */
   #define _INT_PRI_E2                  LEVEL1