📄 mb90590.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 30/01/03 TIME: 11:25:19 AM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 01.02.99 1.0 TKA - created */
/* 18.02.99 1.2 HLO */
/* - ICR now included (icr.h) */
/* - IO-Wizard 1.7 uses IO_EXTENDED now */
/* - WTBR now included (wtbr.h) */
/* 09.04.99 1.3 HLO - '_' removed from "!I"-symbols, now done by IO-Wizard */
/* 14.04.99 1.4 JRO - generation of header and c file with IO-Wizard V 1.9 */
/* 22.04.99 1.5 VSA - Bitdefinitions for parallelports are changed to Pxx, Dxx */
/* 06.05.99 1.6 HLO */
/* - disclaimer added */
/* - unspecified registers removed */
/* 15.07.99 1.7 VSA - PADRx 3 are renamed to PADRx_L 1, PADRx_H 1, PADRx_H 1 */
/* 10.08.99 1.8 VSA - WTCR low and high bytes are exchanged */
/* 23.08.99 1.9 VSA - SMCS bitdefinitions are modified */
/* 03.07.00 1.10 VSA - ADC unit included (adc_01.h) */
/* 01.11.00 1.11 NMP - ADC Structure realignment */
/* 06.03.01 1.12 HLO - ADC dummy bit before STS (using correct ADC_01.h) */
/* 21.02.02 - HWE - Bit groups defined for PWCn */
/* 23.07.02 1.13 HWe - new adc_01.h, icr.h (RMW-Problem) */
/* 09.12.02 1.14 HWe - Register CDCR: Bit MD added */
/* 30.01.03 1.15 HWe - wordaccess to PPGCx/y: PPGC01, .. , PPGCAB */
/* 30.01.03 - wordaccess to PPG Reload: PRL0, .. , PRLB */
/* 30.01.03 - longwordaccess to PPG Reload: PRL01, .. , PRLAB */
.PROGRAM MB90590
.TITLE MB90590
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pdr7, __pdr8, __pdr9, __ddr0, __ddr1
.GLOBAL __ddr2, __ddr3, __ddr4, __ddr5, __ddr6, __ddr7
.GLOBAL __ddr8, __ddr9, __res_1, __ader, __umc0, __usr0
.GLOBAL __uidr0, __uodr0, __urd0, __umc1, __usr1, __uidr1
.GLOBAL __uodr1, __urd1, __umc2, __usr2, __uidr2, __uodr2
.GLOBAL __urd2, __smcs, __sdr, __ses, __enir, __eirr
.GLOBAL __elvr, __adcs, __adcs0, __adcs1, __adcr, __adcr0
.GLOBAL __adcr1, __ppgc01, __ppgc0, __ppgc1, __ppg01, __ppgc23
.GLOBAL __ppgc2, __ppgc3, __ppg23, __ppgc45, __ppgc4, __ppgc5
.GLOBAL __ppg45, __ppgc67, __ppgc6, __ppgc7, __ppg67, __ppgc89
.GLOBAL __ppgc8, __ppgc9, __ppg89, __ppgcab, __ppgca, __ppgcb
.GLOBAL __ppgab, __tmcsr0, __tmcsr1, __ics01, __ics23, __ics45
.GLOBAL __ocs01, __ocs0, __ocs1, __ocs23, __ocs2, __ocs3
.GLOBAL __ocs45, __ocs4, __ocs5, __sgcr, __wtcr, __pwc0
.GLOBAL __pwc1, __pwc2, __pwc3, __cdcr, __tccs, __romm
.GLOBAL __canl0, __canl1, __pacsr, __dirr, __lpmcr, __ckscr
.GLOBAL __wdtc, __tbtc, __fmcs, __icr
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
__pdr7 .res.b 1 ;000007
PDR7 .equ 0x0007
__pdr8 .res.b 1 ;000008
PDR8 .equ 0x0008
__pdr9 .res.b 1 ;000009
PDR9 .equ 0x0009
.org 0x0010
__ddr0 .res.b 1 ;000010 /* PORT DIRECTION */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ddr7 .res.b 1 ;000017
DDR7 .equ 0x0017
__ddr8 .res.b 1 ;000018
DDR8 .equ 0x0018
__ddr9 .res.b 1 ;000019
DDR9 .equ 0x0019
__res_1 .res.b 1 ;00001A
RES_1 .equ 0x001A
__ader .res.b 1 ;00001B
ADER .equ 0x001B
.org 0x0020
__umc0 .res.b 1 ;000020 /* UART0 */
UMC0 .equ 0x0020
__usr0 .res.b 1 ;000021
USR0 .equ 0x0021
__uidr0 .res.b 1 ;000022
UIDR0 .equ 0x0022
.org 0x0022
__uodr0 .res.b 1 ;000022
UODR0 .equ 0x0022
__urd0 .res.b 1 ;000023
URD0 .equ 0x0023
__umc1 .res.b 1 ;000024 /* UART1 */
UMC1 .equ 0x0024
__usr1 .res.b 1 ;000025
USR1 .equ 0x0025
__uidr1 .res.b 1 ;000026
UIDR1 .equ 0x0026
.org 0x0026
__uodr1 .res.b 1 ;000026
UODR1 .equ 0x0026
__urd1 .res.b 1 ;000027
URD1 .equ 0x0027
__umc2 .res.b 1 ;000028 /* UART2 */
UMC2 .equ 0x0028
__usr2 .res.b 1 ;000029
USR2 .equ 0x0029
__uidr2 .res.b 1 ;00002A
UIDR2 .equ 0x002A
.org 0x002A
__uodr2 .res.b 1 ;00002A
UODR2 .equ 0x002A
__urd2 .res.b 1 ;00002B
URD2 .equ 0x002B
__smcs .res.b 2 ;00002C /* SIO with clock selection */
SMCS .equ 0x002C
__sdr .res.b 1 ;00002E
SDR .equ 0x002E
__ses .res.b 1 ;00002F
SES .equ 0x002F
__enir .res.b 1 ;000030 /* DTP, External Interrupts */
ENIR .equ 0x0030
__eirr .res.b 1 ;000031
EIRR .equ 0x0031
__elvr .res.b 2 ;000032
ELVR .equ 0x0032
__adcs .res.b 2 ;000034 /* AD Converter */
ADCS .equ 0x0034
.org 0x0034
__adcs0 .res.b 1 ;000034
ADCS0 .equ 0x0034
__adcs1 .res.b 1 ;000035
ADCS1 .equ 0x0035
__adcr .res.b 2 ;000036
ADCR .equ 0x0036
.org 0x0036
__adcr0 .res.b 1 ;000036
ADCR0 .equ 0x0036
__adcr1 .res.b 1 ;000037
ADCR1 .equ 0x0037
__ppgc01 .res.b 2 ;000038 /* PPG control */
PPGC01 .equ 0x0038
.org 0x0038
__ppgc0 .res.b 1 ;000038
PPGC0 .equ 0x0038
__ppgc1 .res.b 1 ;000039
PPGC1 .equ 0x0039
__ppg01 .res.b 1 ;00003A
PPG01 .equ 0x003A
.org 0x003C
__ppgc23 .res.b 2 ;00003C
PPGC23 .equ 0x003C
.org 0x003C
__ppgc2 .res.b 1 ;00003C
PPGC2 .equ 0x003C
__ppgc3 .res.b 1 ;00003D
PPGC3 .equ 0x003D
__ppg23 .res.b 1 ;00003E
PPG23 .equ 0x003E
.org 0x0040
__ppgc45 .res.b 2 ;000040
PPGC45 .equ 0x0040
.org 0x0040
__ppgc4 .res.b 1 ;000040
PPGC4 .equ 0x0040
__ppgc5 .res.b 1 ;000041
PPGC5 .equ 0x0041
__ppg45 .res.b 1 ;000042
PPG45 .equ 0x0042
.org 0x0044
__ppgc67 .res.b 2 ;000044
PPGC67 .equ 0x0044
.org 0x0044
__ppgc6 .res.b 1 ;000044
PPGC6 .equ 0x0044
__ppgc7 .res.b 1 ;000045
PPGC7 .equ 0x0045
__ppg67 .res.b 1 ;000046
PPG67 .equ 0x0046
.org 0x0048
__ppgc89 .res.b 2 ;000048
PPGC89 .equ 0x0048
.org 0x0048
__ppgc8 .res.b 1 ;000048
PPGC8 .equ 0x0048
__ppgc9 .res.b 1 ;000049
PPGC9 .equ 0x0049
__ppg89 .res.b 1 ;00004A
PPG89 .equ 0x004A
.org 0x004C
__ppgcab .res.b 2 ;00004C
PPGCAB .equ 0x004C
.org 0x004C
__ppgca .res.b 1 ;00004C
PPGCA .equ 0x004C
__ppgcb .res.b 1 ;00004D
PPGCB .equ 0x004D
__ppgab .res.b 1 ;00004E
PPGAB .equ 0x004E
.org 0x0050
__tmcsr0 .res.b 2 ;000050 /* Reload Timer */
TMCSR0 .equ 0x0050
__tmcsr1 .res.b 2 ;000052
TMCSR1 .equ 0x0052
__ics01 .res.b 1 ;000054 /* Input Capture */
ICS01 .equ 0x0054
__ics23 .res.b 1 ;000055
ICS23 .equ 0x0055
__ics45 .res.b 1 ;000056
ICS45 .equ 0x0056
.org 0x0058
__ocs01 .res.b 2 ;000058 /* Output compare */
OCS01 .equ 0x0058
.org 0x0058
__ocs0 .res.b 1 ;000058
OCS0 .equ 0x0058
__ocs1 .res.b 1 ;000059
OCS1 .equ 0x0059
__ocs23 .res.b 2 ;00005A
OCS23 .equ 0x005A
.org 0x005A
__ocs2 .res.b 1 ;00005A
OCS2 .equ 0x005A
__ocs3 .res.b 1 ;00005B
OCS3 .equ 0x005B
__ocs45 .res.b 2 ;00005C
OCS45 .equ 0x005C
.org 0x005C
__ocs4 .res.b 1 ;00005C
OCS4 .equ 0x005C
__ocs5 .res.b 1 ;00005D
OCS5 .equ 0x005D
__sgcr .res.b 2 ;00005E /* Sound control */
SGCR .equ 0x005E
__wtcr .res.b 2 ;000060 /* Watch Timer */
WTCR .equ 0x0060
__pwc0 .res.b 1 ;000062 /* PWM0 */
PWC0 .equ 0x0062
.org 0x0064
__pwc1 .res.b 1 ;000064
PWC1 .equ 0x0064
.org 0x0066
__pwc2 .res.b 1 ;000066
PWC2 .equ 0x0066
.org 0x0068
__pwc3 .res.b 1 ;000068
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