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📄 mb90560.h

📁 富士通单片机MB90F387上实现MODBUS
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    IO_BYTE	byte;
    struct{
    IO_BYTE OTD0 :1;
    IO_BYTE OTD1 :1;
    IO_BYTE OTE0 :1;
    IO_BYTE OTE1 :1;
    IO_BYTE CMOD :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
  }bit;
 }OCS5STR;
typedef union{   /* 16-Bit Reload Timer */
    IO_WORD	word;
    struct{
    IO_WORD TRG :1;
    IO_WORD CNTE :1;
    IO_WORD UF :1;
    IO_WORD INTE :1;
    IO_WORD RELD :1;
    IO_WORD OUTL :1;
    IO_WORD OUTE :1;
    IO_WORD MOD0 :1;
    IO_WORD MOD1 :1;
    IO_WORD MOD2 :1;
    IO_WORD CSL0 :1;
    IO_WORD CSL1 :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
  }bit;
  struct{
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD MOD :3;
    IO_WORD CSL :2;
  }bitc;
 }TMCR0STR;
typedef union{  
    IO_WORD	word;
    struct{
    IO_WORD TRG :1;
    IO_WORD CNTE :1;
    IO_WORD UF :1;
    IO_WORD INTE :1;
    IO_WORD RELD :1;
    IO_WORD OUTL :1;
    IO_WORD OUTE :1;
    IO_WORD MOD0 :1;
    IO_WORD MOD1 :1;
    IO_WORD MOD2 :1;
    IO_WORD CSL0 :1;
    IO_WORD CSL1 :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
  }bit;
  struct{
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD MOD :3;
    IO_WORD CSL :2;
  }bitc;
 }TMCSR0STR;
typedef union{  
    IO_WORD	word;
    struct{
    IO_WORD TRG :1;
    IO_WORD CNTE :1;
    IO_WORD UF :1;
    IO_WORD INTE :1;
    IO_WORD RELD :1;
    IO_WORD OUTL :1;
    IO_WORD OUTE :1;
    IO_WORD MOD0 :1;
    IO_WORD MOD1 :1;
    IO_WORD MOD2 :1;
    IO_WORD CSL0 :1;
    IO_WORD CSL1 :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
  }bit;
  struct{
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD MOD :3;
    IO_WORD CSL :2;
  }bitc;
 }TMCR1STR;
typedef union{  
    IO_WORD	word;
    struct{
    IO_WORD TRG :1;
    IO_WORD CNTE :1;
    IO_WORD UF :1;
    IO_WORD INTE :1;
    IO_WORD RELD :1;
    IO_WORD OUTL :1;
    IO_WORD OUTE :1;
    IO_WORD MOD0 :1;
    IO_WORD MOD1 :1;
    IO_WORD MOD2 :1;
    IO_WORD CSL0 :1;
    IO_WORD CSL1 :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
    IO_WORD  :1;
  }bit;
  struct{
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD :1;
    IO_WORD MOD :3;
    IO_WORD CSL :2;
  }bitc;
 }TMCSR1STR;
typedef union{   /* Input Resistance Register */
    IO_BYTE	byte;
    struct{
    IO_BYTE RD00 :1;
    IO_BYTE RD01 :1;
    IO_BYTE RD02 :1;
    IO_BYTE RD03 :1;
    IO_BYTE RD04 :1;
    IO_BYTE RD05 :1;
    IO_BYTE RD06 :1;
    IO_BYTE RD07 :1;
  }bit;
 }RDR0STR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE RD10 :1;
    IO_BYTE RD11 :1;
    IO_BYTE RD12 :1;
    IO_BYTE RD13 :1;
    IO_BYTE RD14 :1;
    IO_BYTE RD15 :1;
    IO_BYTE RD16 :1;
    IO_BYTE RD17 :1;
  }bit;
 }RDR1STR;
typedef union{   /* rom cORRECTION Function */
    IO_BYTE	byte;
    struct{
    IO_BYTE AD0D :1;
    IO_BYTE AD0E :1;
    IO_BYTE AD1D :1;
    IO_BYTE AD1E :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
  }bit;
 }PACSRSTR;
typedef union{   /* Delayed Interrupt */
    IO_BYTE	byte;
    struct{
    IO_BYTE R0 :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
  }bit;
 }DIRRSTR;
typedef union{   /* Low Power Control Registers */
    IO_BYTE	byte;
    struct{
    IO_BYTE RESV1 :1;
    IO_BYTE CG0 :1;
    IO_BYTE CG1 :1;
    IO_BYTE RESV2 :1;
    IO_BYTE RST :1;
    IO_BYTE SPL :1;
    IO_BYTE SLP :1;
    IO_BYTE STP :1;
  }bit;
  struct{
    IO_BYTE :1;
    IO_BYTE CG :2;
  }bitc;
 }LPMCRSTR;
typedef union{  
    IO_BYTE	byte;
    struct{
    IO_BYTE CS0 :1;
    IO_BYTE CS1 :1;
    IO_BYTE MCS :1;
    IO_BYTE RESV1 :1;
    IO_BYTE WS0 :1;
    IO_BYTE WS1 :1;
    IO_BYTE MCM :1;
    IO_BYTE RESV2 :1;
  }bit;
  struct{
    IO_BYTE CS :2;
    IO_BYTE :1;
    IO_BYTE :1;
    IO_BYTE WS :2;
  }bitc;
 }CKSCRSTR;
typedef union{   /* Watch Dog */
    IO_BYTE	byte;
    struct{
    IO_BYTE WT0 :1;
    IO_BYTE WT1 :1;
    IO_BYTE WTE :1;
    IO_BYTE SRST :1;
    IO_BYTE ERST :1;
    IO_BYTE WRST :1;
    IO_BYTE  :1;
    IO_BYTE PONR :1;
  }bit;
  struct{
    IO_BYTE WT :2;
  }bitc;
 }WDTCSTR;
typedef union{   /* Time Base Timer */
    IO_BYTE	byte;
    struct{
    IO_BYTE TBC0 :1;
    IO_BYTE TBC1 :1;
    IO_BYTE TBR :1;
    IO_BYTE TBOF :1;
    IO_BYTE TBIE :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE RESV :1;
  }bit;
  struct{
    IO_BYTE TBC :2;
  }bitc;
 }TBTCSTR;
typedef union{   /* Flash Control Register */
    IO_BYTE	byte;
    struct{
    IO_BYTE LPM :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE  :1;
    IO_BYTE RDY :1;
    IO_BYTE WE :1;
    IO_BYTE RDYI :1;
    IO_BYTE INTE :1;
  }bit;
 }FMCSSTR;

/* C-DECLARATIONS */

__IO_EXTERN __io PDR0STR _pdr0;   /*  PORT DATA */
#define PDR0 _pdr0.byte
#define PDR0_P00 _pdr0.bit.P00
#define PDR0_P01 _pdr0.bit.P01
#define PDR0_P02 _pdr0.bit.P02
#define PDR0_P03 _pdr0.bit.P03
#define PDR0_P04 _pdr0.bit.P04
#define PDR0_P05 _pdr0.bit.P05
#define PDR0_P06 _pdr0.bit.P06
#define PDR0_P07 _pdr0.bit.P07
__IO_EXTERN __io PDR1STR _pdr1;  
#define PDR1 _pdr1.byte
#define PDR1_P10 _pdr1.bit.P10
#define PDR1_P11 _pdr1.bit.P11
#define PDR1_P12 _pdr1.bit.P12
#define PDR1_P13 _pdr1.bit.P13
#define PDR1_P14 _pdr1.bit.P14
#define PDR1_P15 _pdr1.bit.P15
#define PDR1_P16 _pdr1.bit.P16
#define PDR1_P17 _pdr1.bit.P17
__IO_EXTERN __io PDR2STR _pdr2;  
#define PDR2 _pdr2.byte
#define PDR2_P20 _pdr2.bit.P20
#define PDR2_P21 _pdr2.bit.P21
#define PDR2_P22 _pdr2.bit.P22
#define PDR2_P23 _pdr2.bit.P23
#define PDR2_P24 _pdr2.bit.P24
#define PDR2_P25 _pdr2.bit.P25
#define PDR2_P26 _pdr2.bit.P26
#define PDR2_P27 _pdr2.bit.P27
__IO_EXTERN __io PDR3STR _pdr3;  
#define PDR3 _pdr3.byte
#define PDR3_P30 _pdr3.bit.P30
#define PDR3_P31 _pdr3.bit.P31
#define PDR3_P32 _pdr3.bit.P32
#define PDR3_P33 _pdr3.bit.P33
#define PDR3_P34 _pdr3.bit.P34
#define PDR3_P35 _pdr3.bit.P35
#define PDR3_P36 _pdr3.bit.P36
#define PDR3_P37 _pdr3.bit.P37
__IO_EXTERN __io PDR4STR _pdr4;  
#define PDR4 _pdr4.byte
#define PDR4_P40 _pdr4.bit.P40
#define PDR4_P41 _pdr4.bit.P41
#define PDR4_P42 _pdr4.bit.P42
#define PDR4_P43 _pdr4.bit.P43
#define PDR4_P44 _pdr4.bit.P44
#define PDR4_P45 _pdr4.bit.P45
#define PDR4_P46 _pdr4.bit.P46
#define PDR4_P47 _pdr4.bit.P47
__IO_EXTERN __io PDR5STR _pdr5;  
#define PDR5 _pdr5.byte
#define PDR5_P50 _pdr5.bit.P50
#define PDR5_P51 _pdr5.bit.P51
#define PDR5_P52 _pdr5.bit.P52
#define PDR5_P53 _pdr5.bit.P53
#define PDR5_P54 _pdr5.bit.P54
#define PDR5_P55 _pdr5.bit.P55
#define PDR5_P56 _pdr5.bit.P56
#define PDR5_P57 _pdr5.bit.P57
__IO_EXTERN __io PDR6STR _pdr6;  
#define PDR6 _pdr6.byte
#define PDR6_P60 _pdr6.bit.P60
#define PDR6_P61 _pdr6.bit.P61
#define PDR6_P62 _pdr6.bit.P62
#define PDR6_P63 _pdr6.bit.P63
#define PDR6_P64 _pdr6.bit.P64
#define PDR6_P65 _pdr6.bit.P65
#define PDR6_P66 _pdr6.bit.P66
#define PDR6_P67 _pdr6.bit.P67
__IO_EXTERN __io DDR0STR _ddr0;   /* PORT DIR */
#define DDR0 _ddr0.byte
#define DDR0_D00 _ddr0.bit.D00
#define DDR0_D01 _ddr0.bit.D01
#define DDR0_D02 _ddr0.bit.D02
#define DDR0_D03 _ddr0.bit.D03
#define DDR0_D04 _ddr0.bit.D04
#define DDR0_D05 _ddr0.bit.D05
#define DDR0_D06 _ddr0.bit.D06
#define DDR0_D07 _ddr0.bit.D07
__IO_EXTERN __io DDR1STR _ddr1;  
#define DDR1 _ddr1.byte
#define DDR1_D10 _ddr1.bit.D10
#define DDR1_D11 _ddr1.bit.D11
#define DDR1_D12 _ddr1.bit.D12
#define DDR1_D13 _ddr1.bit.D13
#define DDR1_D14 _ddr1.bit.D14
#define DDR1_D15 _ddr1.bit.D15
#define DDR1_D16 _ddr1.bit.D16
#define DDR1_D17 _ddr1.bit.D17
__IO_EXTERN __io DDR2STR _ddr2;  
#define DDR2 _ddr2.byte
#define DDR2_D20 _ddr2.bit.D20
#define DDR2_D21 _ddr2.bit.D21
#define DDR2_D22 _ddr2.bit.D22
#define DDR2_D23 _ddr2.bit.D23
#define DDR2_D24 _ddr2.bit.D24
#define DDR2_D25 _ddr2.bit.D25
#define DDR2_D26 _ddr2.bit.D26
#define DDR2_D27 _ddr2.bit.D27
__IO_EXTERN __io DDR3STR _ddr3;  
#define DDR3 _ddr3.byte
#define DDR3_D30 _ddr3.bit.D30
#define DDR3_D31 _ddr3.bit.D31
#define DDR3_D32 _ddr3.bit.D32
#define DDR3_D33 _ddr3.bit.D33
#define DDR3_D34 _ddr3.bit.D34
#define DDR3_D35 _ddr3.bit.D35
#define DDR3_D36 _ddr3.bit.D36
#define DDR3_D37 _ddr3.bit.D37
__IO_EXTERN __io DDR4STR _ddr4;  
#define DDR4 _ddr4.byte
#define DDR4_D40 _ddr4.bit.D40
#define DDR4_D41 _ddr4.bit.D41
#define DDR4_D42 _ddr4.bit.D42
#define DDR4_D43 _ddr4.bit.D43
#define DDR4_D44 _ddr4.bit.D44
#define DDR4_D45 _ddr4.bit.D45
#define DDR4_D46 _ddr4.bit.D46
#define DDR4_D47 _ddr4.bit.D47
__IO_EXTERN __io DDR5STR _ddr5;  
#define DDR5 _ddr5.byte
#define DDR5_D50 _ddr5.bit.D50
#define DDR5_D51 _ddr5.bit.D51
#define DDR5_D52 _ddr5.bit.D52
#define DDR5_D53 _ddr5.bit.D53
#define DDR5_D54 _ddr5.bit.D54
#define DDR5_D55 _ddr5.bit.D55
#define DDR5_D56 _ddr5.bit.D56
#define DDR5_D57 _ddr5.bit.D57
__IO_EXTERN __io DDR6STR _ddr6;  
#define DDR6 _ddr6.byte
#define DDR6_D60 _ddr6.bit.D60
#define DDR6_D61 _ddr6.bit.D61
#define DDR6_D62 _ddr6.bit.D62
#define DDR6_D63 _ddr6.bit.D63
#define DDR6_D64 _ddr6.bit.D64
#define DDR6_D65 _ddr6.bit.D65
#define DDR6_D66 _ddr6.bit.D66
#define DDR6_D67 _ddr6.bit.D67
__IO_EXTERN __io ADERSTR _ader;   /* Analog Input Enable Register */
#define ADER _ader.byte
#define ADER_AE0 _ader.bit.AE0
#define ADER_AE1 _ader.bit.AE1
#define ADER_AE2 _ader.bit.AE2
#define ADER_AE3 _ader.bit.AE3
#define ADER_AE4 _ader.bit.AE4
#define ADER_AE5 _ader.bit.AE5
#define ADER_AE6 _ader.bit.AE6
#define ADER_AE7 _ader.bit.AE7
__IO_EXTERN __io SMR0STR _smr0;   /* UART0,1 */
#define SMR0 _smr0.byte
#define SMR0_SOE _smr0.bit.SOE
#define SMR0_SCKE _smr0.bit.SCKE
#define SMR0_BCH _smr0.bit.BCH
#define SMR0_CS0 _smr0.bit.CS0
#define SMR0_CS1 _smr0.bit.CS1
#define SMR0_CS2 _smr0.bit.CS2
#define SMR0_MD0 _smr0.bit.MD0
#define SMR0_MD1 _smr0.bit.MD1
#define SMR0_CS _smr0.bitc.CS
#define SMR0_MD _smr0.bitc.MD
__IO_EXTERN __io SCR0STR _scr0;  
#define SCR0 _scr0.byte
#define SCR0_TXE _scr0.bit.TXE
#define SCR0_RXE _scr0.bit.RXE
#define SCR0_REC _scr0.bit.REC
#define SCR0_AD _scr0.bit.AD
#define SCR0_CL _scr0.bit.CL
#define SCR0_SBL _scr0.bit.SBL
#define SCR0_P _scr0.bit.P
#define SCR0_PEN _scr0.bit.PEN
__IO_EXTERN __io SIDR0STR _sidr0;  
#define SIDR0 _sidr0.byte
__IO_EXTERN __io IO_BYTE _sodr0;
#define SODR0 _sodr0   
__IO_EXTERN __io SSR0STR _ssr0;  
#define SSR0 _ssr0.byte
#define SSR0_TIE _ssr0.bit.TIE
#define SSR0_RIE _ssr0.bit.RIE
#define SSR0_BDS _ssr0.bit.BDS
#define SSR0_TDRE _ssr0.bit.TDRE
#define SSR0_RDRF _ssr0.bit.RDRF
#define SSR0_FRE _ssr0.bit.FRE
#define SSR0_ORE _ssr0.bit.ORE
#define SSR0_PE _ssr0.bit.PE
__IO_EXTERN __io SMR1STR _smr1;  
#define SMR1 _smr1.byte
#define SMR1_SOE _smr1.bit.SOE
#define SMR1_SCKE _smr1.bit.SCKE
#define SMR1_BCH _smr1.bit.BCH
#define SMR1_CS0 _smr1.bit.CS0
#define SMR1_CS1 _smr1.bit.CS1
#define SMR1_CS2 _smr1.bit.CS2
#define SMR1_MD0 _smr1.bit.MD0
#define SMR1_MD1 _smr1.bit.MD1
#define SMR1_CS _smr1.bitc.CS
#define SMR1_MD _smr1.bitc.MD
__IO_EXTERN __io SCR1STR _scr1;  
#define SCR1 _scr1.byte
#define SCR1_TXE _scr1.bit.TXE
#define SCR1_RXE _scr1.bit.RXE
#define SCR1_REC _scr1.bit.REC
#define SCR1_AD _scr1.bit.AD
#define SCR1_CL _scr1.bit.CL
#define SCR1_SBL _scr1.bit.SBL
#define SCR1_P _scr1.bit.P
#define SCR1_PEN _scr1.bit.PEN
__IO_EXTERN __io SIDR1STR _sidr1;  
#define SIDR1 _sidr1.byte
__IO_EXTERN __io IO_BYTE _sodr1;
#define SODR1 _sodr1   
__IO_EXTERN __io SSR1STR _ssr1;  
#define SSR1 _ssr1.byte
#define SSR1_TIE _ssr1.bit.TIE
#define SSR1_RIE _ssr1.bit.RIE
#define SSR1_BDS _ssr1.bit.BDS
#define SSR1_TDRE _ssr1.bit.TDRE
#define SSR1_RDRF _ssr1.bit.RDRF
#define SSR1_FRE _ssr1.bit.FRE
#define SSR1_ORE _ssr1.bit.ORE
#define SSR1_PE _ssr1.bit.PE
__IO_EXTERN __io CDCR0STR _cdcr0;  
#define CDCR0 _cdcr0.byte
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