📄 mb90390.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 1/30/2003 TIME: 4:24:02 PM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 01.06.01 1.0 NMP created */
/* 27.06.01 1.1 NMP - Internal Version only */
/* - Awaiting full register description */
/* before header file complete */
/* 03.08.01 1.2 NMP - Update Clock Module, UART3, ICU */
/* Awaiting full register description */
/* 30.10.01 1.3 HW - taken last version from Neil 31.8.01 and compared to HWM0.5 */
/* TCCS0,1 : CLK2 added */
/* SDR4, CDCR4 : corrected */
/* ELVR : Bitdescription added */
/* OCSx : CMOD0, CMOD1 added */
/* OCS6,7 : Bitdescription added */
/* WTCR : TST0,1,2 removed */
/* ZPDx : Bitdescription added */
/* LPMCR : Bitdescription added */
/* PACSR1 : corrected */
/* RDR3,TDR3 : Bitdescription added */
/* CANSWR : Bitdescription added */
/* CDMR : Bitdescription added */
/* IDBL (Adr:35AB) 1 DBL deleted */
/* ICCR : Adress corrected 35AC => 35AB */
/* ICE01,ICE45 Bit renamed ISS => IUCE */
/* ICE45 : Adress corrected 35CC => 35CB */
/* ROM correction PADR3,4,5 added */
/* 20.11.01 1.3 HW - wordacess to: PPGC01, PPGC23, PPGC45, PPGC67, PPGC89, PGCAB */
/* 28.01.02 1.4 HW - CDCR4, SMCS4, SDR4 => renamed: CDCR, SMCS, SDR */
/* LPMCR: Bit 0 (SSR) deleted */
/* ADER1 added */
/* 30.01.03 1.5 HWE - wordaccess to PPG Reload: PRL0, PRL1, PRL2, .. , PRLB */
/* HWE - longwordaccess to PPG Reload: PRL01, PRL23, .. , PRLAB */
/* HWE - PPGC bit-definitions corrected */
/* HWE - CKOE Bitdefinition changed: CKOE=>OE, CKXOE=>XOE */
/* */
.PROGRAM MB90390
.TITLE MB90390
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pdr7, __pdr8, __pdr9, __pdra, __pdrb
.GLOBAL __ader0, __ader1, __ilsr, __ddr0, __ddr1, __ddr2
.GLOBAL __ddr3, __ddr4, __ddr5, __ddr6, __ddr7, __ddr8
.GLOBAL __ddr9, __ddra, __ddrb, __umc0, __usr0, __uidr0
.GLOBAL __uodr0, __urd0, __umc1, __usr1, __uidr1, __uodr1
.GLOBAL __urd1, __umc2, __usr2, __uidr2, __uodr2, __urd2
.GLOBAL __smcs, __sdr, __cdcr, __enir, __eirr, __elvr
.GLOBAL __adcs, __adcs0, __adcs1, __adcr, __adcr0, __adcr1
.GLOBAL __ppgc01, __ppgc0, __ppgc1, __ppg01, __pacsr1, __ppgc23
.GLOBAL __ppgc2, __ppgc3, __ppg23, __ckoe, __ppgc45, __ppgc4
.GLOBAL __ppgc5, __ppg45, __ppgc67, __ppgc6, __ppgc7, __ppg67
.GLOBAL __ppgc89, __ppgc8, __ppgc9, __ppg89, __ppgcab, __ppgca
.GLOBAL __ppgcb, __ppgab, __tmcsr0, __tmcsr1, __ics01, __ics23
.GLOBAL __ics45, __ocs01, __ocs0, __ocs1, __ocs23, __ocs2
.GLOBAL __ocs3, __ocs45, __ocs4, __ocs5, __sgcr, __wtcr
.GLOBAL __pwc0, __zpd0, __pwc1, __zpd1, __pwc2, __zpd2
.GLOBAL __pwc3, __zpd3, __pwc4, __zpd4, __pwc5, __zpd5
.GLOBAL __romm, __canl0, __canl1, __pacsr0, __dirr, __lpmcr
.GLOBAL __ckscr, __wdtc, __tbtc, __fmcs, __icr
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
__pdr7 .res.b 1 ;000007
PDR7 .equ 0x0007
__pdr8 .res.b 1 ;000008
PDR8 .equ 0x0008
__pdr9 .res.b 1 ;000009
PDR9 .equ 0x0009
__pdra .res.b 1 ;00000A
PDRA .equ 0x000A
__pdrb .res.b 1 ;00000B
PDRB .equ 0x000B
__ader0 .res.b 1 ;00000C
ADER0 .equ 0x000C
__ader1 .res.b 1 ;00000D
ADER1 .equ 0x000D
__ilsr .res.b 2 ;00000E
ILSR .equ 0x000E
__ddr0 .res.b 1 ;000010 /* PORT DIRECTION */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ddr7 .res.b 1 ;000017
DDR7 .equ 0x0017
__ddr8 .res.b 1 ;000018
DDR8 .equ 0x0018
__ddr9 .res.b 1 ;000019
DDR9 .equ 0x0019
__ddra .res.b 1 ;00001A
DDRA .equ 0x001A
__ddrb .res.b 1 ;00001B
DDRB .equ 0x001B
.org 0x0020
__umc0 .res.b 1 ;000020 /* UART0 */
UMC0 .equ 0x0020
__usr0 .res.b 1 ;000021
USR0 .equ 0x0021
__uidr0 .res.b 1 ;000022
UIDR0 .equ 0x0022
.org 0x0022
__uodr0 .res.b 1 ;000022
UODR0 .equ 0x0022
__urd0 .res.b 1 ;000023
URD0 .equ 0x0023
__umc1 .res.b 1 ;000024 /* UART1 */
UMC1 .equ 0x0024
__usr1 .res.b 1 ;000025
USR1 .equ 0x0025
__uidr1 .res.b 1 ;000026
UIDR1 .equ 0x0026
.org 0x0026
__uodr1 .res.b 1 ;000026
UODR1 .equ 0x0026
__urd1 .res.b 1 ;000027
URD1 .equ 0x0027
__umc2 .res.b 1 ;000028 /* UART2 */
UMC2 .equ 0x0028
__usr2 .res.b 1 ;000029
USR2 .equ 0x0029
__uidr2 .res.b 1 ;00002A
UIDR2 .equ 0x002A
.org 0x002A
__uodr2 .res.b 1 ;00002A
UODR2 .equ 0x002A
__urd2 .res.b 1 ;00002B
URD2 .equ 0x002B
__smcs .res.b 2 ;00002C /* SIO with clock selection */
SMCS .equ 0x002C
__sdr .res.b 1 ;00002E
SDR .equ 0x002E
__cdcr .res.b 1 ;00002F
CDCR .equ 0x002F
__enir .res.b 1 ;000030 /* DTP, External Interrupts */
ENIR .equ 0x0030
__eirr .res.b 1 ;000031
EIRR .equ 0x0031
__elvr .res.b 2 ;000032
ELVR .equ 0x0032
__adcs .res.b 2 ;000034 /* AD Converter */
ADCS .equ 0x0034
.org 0x0034
__adcs0 .res.b 1 ;000034
ADCS0 .equ 0x0034
__adcs1 .res.b 1 ;000035
ADCS1 .equ 0x0035
__adcr .res.b 2 ;000036
ADCR .equ 0x0036
.org 0x0036
__adcr0 .res.b 1 ;000036
ADCR0 .equ 0x0036
__adcr1 .res.b 1 ;000037
ADCR1 .equ 0x0037
__ppgc01 .res.b 2 ;000038 /* PPG control */
PPGC01 .equ 0x0038
.org 0x0038
__ppgc0 .res.b 1 ;000038
PPGC0 .equ 0x0038
__ppgc1 .res.b 1 ;000039
PPGC1 .equ 0x0039
__ppg01 .res.b 1 ;00003A
PPG01 .equ 0x003A
__pacsr1 .res.b 1 ;00003B /* Rom Correction 1 */
PACSR1 .equ 0x003B
__ppgc23 .res.b 2 ;00003C
PPGC23 .equ 0x003C
.org 0x003C
__ppgc2 .res.b 1 ;00003C
PPGC2 .equ 0x003C
__ppgc3 .res.b 1 ;00003D
PPGC3 .equ 0x003D
__ppg23 .res.b 1 ;00003E
PPG23 .equ 0x003E
__ckoe .res.b 1 ;00003F
CKOE .equ 0x003F
__ppgc45 .res.b 2 ;000040
PPGC45 .equ 0x0040
.org 0x0040
__ppgc4 .res.b 1 ;000040
PPGC4 .equ 0x0040
__ppgc5 .res.b 1 ;000041
PPGC5 .equ 0x0041
__ppg45 .res.b 1 ;000042
PPG45 .equ 0x0042
.org 0x0044
__ppgc67 .res.b 2 ;000044
PPGC67 .equ 0x0044
.org 0x0044
__ppgc6 .res.b 1 ;000044
PPGC6 .equ 0x0044
__ppgc7 .res.b 1 ;000045
PPGC7 .equ 0x0045
__ppg67 .res.b 1 ;000046
PPG67 .equ 0x0046
.org 0x0048
__ppgc89 .res.b 2 ;000048
PPGC89 .equ 0x0048
.org 0x0048
__ppgc8 .res.b 1 ;000048
PPGC8 .equ 0x0048
__ppgc9 .res.b 1 ;000049
PPGC9 .equ 0x0049
__ppg89 .res.b 1 ;00004A
PPG89 .equ 0x004A
.org 0x004C
__ppgcab .res.b 2 ;00004C
PPGCAB .equ 0x004C
.org 0x004C
__ppgca .res.b 1 ;00004C
PPGCA .equ 0x004C
__ppgcb .res.b 1 ;00004D
PPGCB .equ 0x004D
__ppgab .res.b 1 ;00004E
PPGAB .equ 0x004E
.org 0x0050
__tmcsr0 .res.b 2 ;000050 /* Reload Timer */
TMCSR0 .equ 0x0050
__tmcsr1 .res.b 2 ;000052
TMCSR1 .equ 0x0052
__ics01 .res.b 1 ;000054 /* Input Capture */
ICS01 .equ 0x0054
__ics23 .res.b 1 ;000055
ICS23 .equ 0x0055
__ics45 .res.b 1 ;000056
ICS45 .equ 0x0056
.org 0x0058
__ocs01 .res.b 2 ;000058 /* Output compare */
OCS01 .equ 0x0058
.org 0x0058
__ocs0 .res.b 1 ;000058
OCS0 .equ 0x0058
__ocs1 .res.b 1 ;000059
OCS1 .equ 0x0059
__ocs23 .res.b 2 ;00005A
OCS23 .equ 0x005A
.org 0x005A
__ocs2 .res.b 1 ;00005A
OCS2 .equ 0x005A
__ocs3 .res.b 1 ;00005B
OCS3 .equ 0x005B
__ocs45 .res.b 2 ;00005C
OCS45 .equ 0x005C
.org 0x005C
__ocs4 .res.b 1 ;00005C
OCS4 .equ 0x005C
__ocs5 .res.b 1 ;00005D
OCS5 .equ 0x005D
__sgcr .res.b 2 ;00005E /* Sound control */
SGCR .equ 0x005E
__wtcr .res.b 2 ;000060 /* Watch Timer */
WTCR .equ 0x0060
__pwc0 .res.b 1 ;000062 /* PWM0 */
PWC0 .equ 0x0062
__zpd0 .res.b 1 ;000063
ZPD0 .equ 0x0063
__pwc1 .res.b 1 ;000064
PWC1 .equ 0x0064
__zpd1 .res.b 1 ;000065
ZPD1 .equ 0x0065
__pwc2 .res.b 1 ;000066
PWC2 .equ 0x0066
__zpd2 .res.b 1 ;000067
ZPD2 .equ 0x0067
__pwc3 .res.b 1 ;000068
PWC3 .equ 0x0068
__zpd3 .res.b 1 ;000069
ZPD3 .equ 0x0069
__pwc4 .res.b 1 ;00006A
PWC4 .equ 0x006A
__zpd4 .res.b 1 ;00006B
ZPD4 .equ 0x006B
__pwc5 .res.b 1 ;00006C
PWC5 .equ 0x006C
__zpd5 .res.b 1 ;00006D
ZPD5 .equ 0x006D
.org 0x006F
__romm .res.b 1 ;00006F /* ROM Mirror */
ROMM .equ 0x006F
__canl0 .res.b 0x10 ;000070 /* CAN buffer control, lower part */
CANL0 .equ 0x0070
__canl1 .res.b 0x10 ;000080
CANL1 .equ 0x0080
.org 0x009E
__pacsr0 .res.b 1 ;00009E /* ROM Correction 0 */
PACSR0 .equ 0x009E
__dirr .res.b 1 ;00009F /* Delay interrupt enable */
DIRR .equ 0x009F
__lpmcr .res.b 1 ;0000A0 /* Low power mode control */
LPMCR .equ 0x00A0
__ckscr .res.b 1 ;0000A1 /* Clock selection */
CKSCR .equ 0x00A1
.org 0x00A8
__wdtc .res.b 1 ;0000A8 /* Watchdog Control */
WDTC .equ 0x00A8
__tbtc .res.b 1 ;0000A9 /* Time Base timer */
TBTC .equ 0x00A9
.org 0x00AE
__fmcs .res.b 1 ;0000AE /* Flash Control Register */
FMCS .equ 0x00AE
.org 0x00B0
__icr .res.b 0x10 ;0000B0 /* Interrupt Control Registers */
ICR .equ 0x00B0
.section IOXTND, DATA, locate=0x1FF0 ; /* ROM CORRECTION */
.GLOBAL __padr0_l, __padr0_m, __padr0_h, __padr1_l, __padr1_m, __padr1_h
__padr0_l .res.b 1 ;001FF0 /* ROM CORRECTION */
PADR0_L .equ 0x1FF0
__padr0_m .res.b 1 ;001FF1
PADR0_M .equ 0x1FF1
__padr0_h .res.b 1 ;001FF2
PADR0_H .equ 0x1FF2
__padr1_l .res.b 1 ;001FF3
PADR1_L .equ 0x1FF3
__padr1_m .res.b 1 ;001FF4
PADR1_M .equ 0x1FF4
__padr1_h .res.b 1 ;001FF5
PADR1_H .equ 0x1FF5
.section IOXTND2, DATA, locate=0x3500 ; /* PPG data */
.GLOBAL __prl01, __prl0, __prll0, __prlh0, __prl1, __prll1
.GLOBAL __prlh1, __prl23, __prl2, __prll2, __prlh2, __prl3
.GLOBAL __prll3, __prlh3, __prl45, __prl4, __prll4, __prlh4
.GLOBAL __prl5, __prll5, __prlh5, __prl67, __prl6, __prll6
.GLOBAL __prlh6, __prl7, __prll7, __prlh7, __prl89, __prl8
.GLOBAL __prll8, __prlh8, __prl9, __prll9, __prlh9, __prlab
.GLOBAL __prla, __prlla, __prlha, __prlb, __prllb, __prlhb
.GLOBAL __smr3, __scr3, __rdr3, __tdr3, __ssr3, __eccr3
.GLOBAL __escr3, __bgr3, __bgr03, __bgr13, __ipcp0, __ipcp1
.GLOBAL __ipcp2, __ipcp3, __ipcp4, __ipcp5, __tcdt0, __tccs0
.GLOBAL __occp0, __occp1, __occp2, __occp3, __occp4, __occp5
.GLOBAL __tcdt1, __tccs1, __tmr0, __tmrlr0, __tmr1, __tmrlr1
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