📄 mb90520.h
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* SOFTUNE WORKBENCH FORMAT */
/* C-DEFINITIONS FOR IO-SYMBOLS */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 30/01/03 TIME: 2:27:09 PM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 28.01.99 1.0 TKA created with M.Ehlert, Glyn */
/* 14.04.00 1.1 JRO generation of header and c file with IO-Wizard V 1.9 */
/* 27.05.99 1.2 VSA */
/* - disclaimer added */
/* - Bitdefinitions for parallelports are changed to Pxx, Dxx */
/* - 000C OCCP4 -> OCP4 */
/* - 0036 ADCS0 -> ADCS1 */
/* - 0037 ADCS1 -> ADCS2 */
/* - 0038 ADCR0 -> ADCR1 */
/* - 0039 ADCR1 -> ADCR2 */
/* 03.07.00 1.3 VSA ADC unit inluded (adc_12.h) */
/* 01.11.00 1.4 NMP ADC Structure realignment */
/* 08.11.00 1.5 NMP Reduild to remove incorrect comments */
/* 23.07.02 1.6 HWE new icr.h, adc_12.h (RMW-Problem) */
/* 30.01.03 1.7 HWE wordaccess to PPGCx/y: PPGC01 */
/* longwordaccess to PPG Reload: PRL01 */
/* LPMCR Bit0 (SSR) deleted */
#ifndef __MB90XXX_H
# define __MB90XXX_H
/*
- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default
data bank (DTB) is 00. This will result in better performance in these
models.
- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default
data bank (DTB) is other than 00. This might be the case in systems with
external RAM, which are not using internal RAM as default data area.
- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This
will work with almost all configurations.
*/
# ifdef __IO_NEAR
# ifdef __IO_FAR
# error __IO_NEAR and __IO_FAR must not be defined at the same time
# else
# define ___IOWIDTH __near
# endif
# else
# ifdef __IO_FAR
# define ___IOWIDTH __far
# else /* specified by memory model */
# define ___IOWIDTH
# endif
# endif
# ifdef __IO_DEFINE
# define __IO_EXTERN
# define __IO_EXTENDED volatile ___IOWIDTH
# else
# define __IO_EXTERN extern /* for data, which can have __io */
# define __IO_EXTENDED extern volatile ___IOWIDTH
# endif
typedef unsigned char IO_BYTE;
typedef unsigned short IO_WORD;
typedef unsigned long IO_LWORD;
typedef const unsigned short IO_WORD_READ;
/* REGISTER BIT STRUCTURES */
typedef union{ /* PORT DATA Registers */
IO_BYTE byte;
struct{
IO_BYTE P00 :1;
IO_BYTE P01 :1;
IO_BYTE P02 :1;
IO_BYTE P03 :1;
IO_BYTE P04 :1;
IO_BYTE P05 :1;
IO_BYTE P06 :1;
IO_BYTE P07 :1;
}bit;
}PDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P10 :1;
IO_BYTE P11 :1;
IO_BYTE P12 :1;
IO_BYTE P13 :1;
IO_BYTE P14 :1;
IO_BYTE P15 :1;
IO_BYTE P16 :1;
IO_BYTE P17 :1;
}bit;
}PDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P20 :1;
IO_BYTE P21 :1;
IO_BYTE P22 :1;
IO_BYTE P23 :1;
IO_BYTE P24 :1;
IO_BYTE P25 :1;
IO_BYTE P26 :1;
IO_BYTE P27 :1;
}bit;
}PDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P30 :1;
IO_BYTE P31 :1;
IO_BYTE P32 :1;
IO_BYTE P33 :1;
IO_BYTE P34 :1;
IO_BYTE P35 :1;
IO_BYTE P36 :1;
IO_BYTE P37 :1;
}bit;
}PDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P40 :1;
IO_BYTE P41 :1;
IO_BYTE P42 :1;
IO_BYTE P43 :1;
IO_BYTE P44 :1;
IO_BYTE P45 :1;
IO_BYTE P46 :1;
IO_BYTE P47 :1;
}bit;
}PDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P50 :1;
IO_BYTE P51 :1;
IO_BYTE P52 :1;
IO_BYTE P53 :1;
IO_BYTE P54 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}PDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P60 :1;
IO_BYTE P61 :1;
IO_BYTE P62 :1;
IO_BYTE P63 :1;
IO_BYTE P64 :1;
IO_BYTE P65 :1;
IO_BYTE P66 :1;
IO_BYTE P67 :1;
}bit;
}PDR6STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P70 :1;
IO_BYTE P71 :1;
IO_BYTE P72 :1;
IO_BYTE P73 :1;
IO_BYTE P74 :1;
IO_BYTE P75 :1;
IO_BYTE P76 :1;
IO_BYTE P77 :1;
}bit;
}PDR7STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P80 :1;
IO_BYTE P81 :1;
IO_BYTE P82 :1;
IO_BYTE P83 :1;
IO_BYTE P84 :1;
IO_BYTE P85 :1;
IO_BYTE P86 :1;
IO_BYTE P87 :1;
}bit;
}PDR8STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P90 :1;
IO_BYTE P91 :1;
IO_BYTE P92 :1;
IO_BYTE P93 :1;
IO_BYTE P94 :1;
IO_BYTE P95 :1;
IO_BYTE P96 :1;
IO_BYTE P97 :1;
}bit;
}PDR9STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE PA0 :1;
IO_BYTE PA1 :1;
IO_BYTE PA2 :1;
IO_BYTE PA3 :1;
IO_BYTE PA4 :1;
IO_BYTE PA5 :1;
IO_BYTE PA6 :1;
IO_BYTE PA7 :1;
}bit;
}PDRASTR;
typedef union{ /* LCD Pin Switch */
IO_BYTE byte;
struct{
IO_BYTE COM0 :1;
IO_BYTE COM1 :1;
IO_BYTE COM2 :1;
IO_BYTE COM3 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}LCDCMRSTR;
typedef union{ /* WakeUpIntFlag */
IO_BYTE byte;
struct{
IO_BYTE WIF :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}EIFRSTR;
typedef union{ /* PORT DIR */
IO_BYTE byte;
struct{
IO_BYTE D00 :1;
IO_BYTE D01 :1;
IO_BYTE D02 :1;
IO_BYTE D03 :1;
IO_BYTE D04 :1;
IO_BYTE D05 :1;
IO_BYTE D06 :1;
IO_BYTE D07 :1;
}bit;
}DDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D10 :1;
IO_BYTE D11 :1;
IO_BYTE D12 :1;
IO_BYTE D13 :1;
IO_BYTE D14 :1;
IO_BYTE D15 :1;
IO_BYTE D16 :1;
IO_BYTE D17 :1;
}bit;
}DDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D20 :1;
IO_BYTE D21 :1;
IO_BYTE D22 :1;
IO_BYTE D23 :1;
IO_BYTE D24 :1;
IO_BYTE D25 :1;
IO_BYTE D26 :1;
IO_BYTE D27 :1;
}bit;
}DDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D30 :1;
IO_BYTE D31 :1;
IO_BYTE D32 :1;
IO_BYTE D33 :1;
IO_BYTE D34 :1;
IO_BYTE D35 :1;
IO_BYTE D36 :1;
IO_BYTE D37 :1;
}bit;
}DDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D40 :1;
IO_BYTE D41 :1;
IO_BYTE D42 :1;
IO_BYTE D43 :1;
IO_BYTE D44 :1;
IO_BYTE D45 :1;
IO_BYTE D46 :1;
IO_BYTE D47 :1;
}bit;
}DDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D50 :1;
IO_BYTE D51 :1;
IO_BYTE D52 :1;
IO_BYTE D53 :1;
IO_BYTE D54 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}DDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D60 :1;
IO_BYTE D61 :1;
IO_BYTE D62 :1;
IO_BYTE D63 :1;
IO_BYTE D64 :1;
IO_BYTE D65 :1;
IO_BYTE D66 :1;
IO_BYTE D67 :1;
}bit;
}DDR6STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D70 :1;
IO_BYTE D71 :1;
IO_BYTE D72 :1;
IO_BYTE D73 :1;
IO_BYTE D74 :1;
IO_BYTE D75 :1;
IO_BYTE D76 :1;
IO_BYTE D77 :1;
}bit;
}DDR7STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D80 :1;
IO_BYTE D81 :1;
IO_BYTE D82 :1;
IO_BYTE D83 :1;
IO_BYTE D84 :1;
IO_BYTE D85 :1;
IO_BYTE D86 :1;
IO_BYTE D87 :1;
}bit;
}DDR8STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D90 :1;
IO_BYTE D91 :1;
IO_BYTE D92 :1;
IO_BYTE D93 :1;
IO_BYTE D94 :1;
IO_BYTE D95 :1;
IO_BYTE D96 :1;
IO_BYTE D97 :1;
}bit;
}DDR9STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE DA0 :1;
IO_BYTE DA1 :1;
IO_BYTE DA2 :1;
IO_BYTE DA3 :1;
IO_BYTE DA4 :1;
IO_BYTE DA5 :1;
IO_BYTE DA6 :1;
IO_BYTE DA7 :1;
}bit;
}DDRASTR;
typedef union{ /* AnalogInputEnable Port 5 */
IO_BYTE byte;
struct{
IO_BYTE ADE0 :1;
IO_BYTE ADE1 :1;
IO_BYTE ADE2 :1;
IO_BYTE ADE3 :1;
IO_BYTE ADE4 :1;
IO_BYTE ADE5 :1;
IO_BYTE ADE6 :1;
IO_BYTE ADE7 :1;
}bit;
}ADERSTR;
typedef union{ /* WakeUpIntEnable */
IO_BYTE byte;
struct{
IO_BYTE EN0 :1;
IO_BYTE EN1 :1;
IO_BYTE EN2 :1;
IO_BYTE EN3 :1;
IO_BYTE EN4 :1;
IO_BYTE EN5 :1;
IO_BYTE EN6 :1;
IO_BYTE EN7 :1;
}bit;
}EICRSTR;
typedef union{ /* UART */
IO_BYTE byte;
struct{
IO_BYTE SOE :1;
IO_BYTE SCKE :1;
IO_BYTE :1;
IO_BYTE CS0 :1;
IO_BYTE CS1 :1;
IO_BYTE CS2 :1;
IO_BYTE MD0 :1;
IO_BYTE MD1 :1;
}bit;
struct{
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE CS :3;
IO_BYTE MD :2;
}bitc;
}SMRSTR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TXE :1;
IO_BYTE RXE :1;
IO_BYTE REC :1;
IO_BYTE AD :1;
IO_BYTE CL :1;
IO_BYTE SBL :1;
IO_BYTE P :1;
IO_BYTE PEN :1;
}bit;
}SCRSTR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SIDRSTR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SODRSTR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TIE :1;
IO_BYTE RIE :1;
IO_BYTE :1;
IO_BYTE TDRE :1;
IO_BYTE RDRF :1;
IO_BYTE FRE :1;
IO_BYTE ORE :1;
IO_BYTE PE :1;
}bit;
}SSRSTR;
typedef union{ /* SIO channels 0,1 */
IO_WORD word;
struct{
IO_WORD SCOE :1;
IO_WORD SOE :1;
IO_WORD BDS :1;
IO_WORD MODE :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD STRT :1;
IO_WORD STOP :1;
IO_WORD BUSY :1;
IO_WORD SIR :1;
IO_WORD SIE :1;
IO_WORD SMD0 :1;
IO_WORD SMD1 :1;
IO_WORD SMD2 :1;
}bit;
struct{
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD :1;
IO_WORD SMD :3;
}bitc;
}SMCS0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE DIV0 :1;
IO_BYTE DIV1 :1;
IO_BYTE DIV2 :1;
IO_BYTE DIV3 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
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