📄 mb90470.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 29/01/03 TIME: 2:01:33 PM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 31.08.00 1.0 VSA created */
/* 05.09.00 1.1 VSA ... */
/* 21.09.00 1.2 MST TMR/TMRLR address corrected */
/* 01.11.00 1.3 NMP ADC Structure realigned */
/* 15.02.02 1.4 HWe UDER: UDE6,UDE7 deleted */
/* 15.02.02 1.4 HWe TMR0/TMRLR0 renamed to: TMR/TMRLR */
/* 15.02.02 1.4 HWe SDCR0/1 : DIV3 added */
/* 15.02.02 1.4 HWe PPGC2/3/4/5 : Bitnames corrected */
/* 15.02.02 1.4 HWe OCS1/3/5 : Bitdefinition corrected */
/* 15.02.02 1.4 HWe CPCLRL => CPCLR renamed for word-access */
/* 15.02.02 1.4 HWe CPCLRL/CPCLRH added for byte-access */
/* 15.02.02 1.4 HWe CCRL0/1 : UMDC => UDMS renamed */
/* 15.02.02 1.4 HWe CSR0/1 : Bit renamed: OMFF => OVFF */
/* 15.02.02 1.4 HWe IBCR : Bit renamed: BETE => BEIE */
/* 15.02.02 1.4 HWe PGCSR : Bitdefinition corrected */
/* 15.02.02 1.4 HWe DSR, DSRL (0x9C) / DSRH (0x9D) added */
/* 15.02.02 1.4 HWe DSR, DSRL (0xA2) / DSRH (0xA3) deleted */
/* 15.02.02 1.4 HWe address of PDR7 corrected: 06h => 07h */
/* 23.07.02 1.5 HWe new adc_01.h, icr.h (RMW-Problem) */
/* 19.08.02 1.6 HWe bitdefinitions ODR4,ODR7 (CDxx=>ODxx) */
/* SMCS0/1_SCE => SMCS0/1_SOE */
/* Bits grouped SDCR0/1 (DIV0..3) */
/* bitdefinitions CSCR (CPLx=>OPLx) */
/* 01.11.02 1.7 HWe security section added */
/* 29.01.03 1.8 HWe wordaccess to PPG Reload: PRL1, .. , PRL5 */
/* 29.01.03 1.8 HWe longwordaccess to PPG Reload: PRL01, .. , PRL45 */
/* 29.01.03 1.8 HWe Uart0-register renamed: SMR=>SMR0, SCR=>SCR0, */
/* 29.01.03 SIDR=>SIDR0, SODR=>SODR0, SSR=>SSR0 */
/* 29.01.03 1.8 HWe Bitgroup: WTC:[WTC0..WTC2] deleted (name inconsistency) */
.PROGRAM MB90470
.TITLE MB90470
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA Registers */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pdr7, __pdr8, __pdr9, __pdra, __uder
.GLOBAL __enir, __eirr, __elvr, __ddr0, __ddr1, __ddr2
.GLOBAL __ddr3, __ddr4, __ddr5, __ddr6, __ddr7, __ddr8
.GLOBAL __ddr9, __ddra, __odr4, __rdr0, __rdr1, __odr7
.GLOBAL __ader, __smr0, __scr0, __sidr0, __sodr0, __ssr0
.GLOBAL __cdcr, __smcs0, __sdr0, __sdcr0, __smcs1, __sdr1
.GLOBAL __sdcr1, __prl01, __prl0, __prll0, __prlh0, __prl1
.GLOBAL __prll1, __prlh1, __prl23, __prl2, __prll2, __prlh2
.GLOBAL __prl3, __prll3, __prlh3, __prl45, __prl4, __prll4
.GLOBAL __prlh4, __prl5, __prll5, __prlh5, __ppgc01, __ppgc0
.GLOBAL __ppgc1, __ppgc23, __ppgc2, __ppgc3, __ppgc45, __ppgc4
.GLOBAL __ppgc5, __ppg01, __ppg23, __ppg45, __adcs, __adcs1
.GLOBAL __adcs2, __adcr, __adcr1, __adcr2, __occp0, __occp1
.GLOBAL __occp2, __occp3, __occp4, __occp5, __ocs0, __ocs1
.GLOBAL __ocs2, __ocs3, __ocs4, __ocs5, __ipcp0, __ipcp1
.GLOBAL __ics01, __tcdt, __tcdtl, __tcdth, __tccs, __cpclr
.GLOBAL __cpclrl, __cpclrh, __udcr0, __udcr1, __rcr0, __rcr1
.GLOBAL __ccr0, __ccrl0, __ccrh0, __romm, __ccr1, __ccrl1
.GLOBAL __ccrh1, __csr0, __csr1, __pwcsr0, __pwcr0, __pwcsr1
.GLOBAL __pwcr1, __pwcsr2, __pwcr2, __divr0, __divr1, __divr2
.GLOBAL __ibsr, __ibcr, __iccr, __iadr, __idar, __pgcsr
.GLOBAL __dsr, __dsrl, __dsrh, __dirr, __lpmcr, __ckscr
.GLOBAL __dssr, __arsr, __hacr, __ecsr, __wdtc, __tbtc
.GLOBAL __wtc, __der, __derl, __derh, __fmcs, __icr
.GLOBAL __cmr0, __car0, __cmr1, __car1, __cmr2, __car2
.GLOBAL __cmr3, __car3, __cscr, __calr, __tmcsr, __tmr
.GLOBAL __tmrlr
__pdr0 .res.b 1 ;000000 /* PORT DATA Registers */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
__pdr7 .res.b 1 ;000007
PDR7 .equ 0x0007
__pdr8 .res.b 1 ;000008
PDR8 .equ 0x0008
__pdr9 .res.b 1 ;000009
PDR9 .equ 0x0009
__pdra .res.b 1 ;00000A
PDRA .equ 0x000A
__uder .res.b 1 ;00000B
UDER .equ 0x000B
__enir .res.b 1 ;00000C
ENIR .equ 0x000C
__eirr .res.b 1 ;00000D
EIRR .equ 0x000D
__elvr .res.b 2 ;00000E
ELVR .equ 0x000E
__ddr0 .res.b 1 ;000010 /* PORT DIR */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ddr7 .res.b 1 ;000017
DDR7 .equ 0x0017
__ddr8 .res.b 1 ;000018
DDR8 .equ 0x0018
__ddr9 .res.b 1 ;000019
DDR9 .equ 0x0019
__ddra .res.b 1 ;00001A
DDRA .equ 0x001A
__odr4 .res.b 1 ;00001B
ODR4 .equ 0x001B
__rdr0 .res.b 1 ;00001C
RDR0 .equ 0x001C
__rdr1 .res.b 1 ;00001D
RDR1 .equ 0x001D
__odr7 .res.b 1 ;00001E
ODR7 .equ 0x001E
__ader .res.b 1 ;00001F
ADER .equ 0x001F
__smr0 .res.b 1 ;000020 /* UART0 */
SMR0 .equ 0x0020
__scr0 .res.b 1 ;000021
SCR0 .equ 0x0021
__sidr0 .res.b 1 ;000022
SIDR0 .equ 0x0022
.org 0x0022
__sodr0 .res.b 1 ;000022
SODR0 .equ 0x0022
__ssr0 .res.b 1 ;000023
SSR0 .equ 0x0023
.org 0x0025
__cdcr .res.b 1 ;000025
CDCR .equ 0x0025
__smcs0 .res.b 2 ;000026
SMCS0 .equ 0x0026
__sdr0 .res.b 1 ;000028
SDR0 .equ 0x0028
__sdcr0 .res.b 1 ;000029
SDCR0 .equ 0x0029
__smcs1 .res.b 2 ;00002A
SMCS1 .equ 0x002A
__sdr1 .res.b 1 ;00002C
SDR1 .equ 0x002C
__sdcr1 .res.b 1 ;00002D
SDCR1 .equ 0x002D
__prl01 .res.b 4 ;00002E /* PPG */
PRL01 .equ 0x002E
.org 0x002E
__prl0 .res.b 2 ;00002E
PRL0 .equ 0x002E
.org 0x002E
__prll0 .res.b 1 ;00002E
PRLL0 .equ 0x002E
__prlh0 .res.b 1 ;00002F
PRLH0 .equ 0x002F
__prl1 .res.b 2 ;000030
PRL1 .equ 0x0030
.org 0x0030
__prll1 .res.b 1 ;000030
PRLL1 .equ 0x0030
__prlh1 .res.b 1 ;000031
PRLH1 .equ 0x0031
__prl23 .res.b 4 ;000032
PRL23 .equ 0x0032
.org 0x0032
__prl2 .res.b 2 ;000032
PRL2 .equ 0x0032
.org 0x0032
__prll2 .res.b 1 ;000032
PRLL2 .equ 0x0032
__prlh2 .res.b 1 ;000033
PRLH2 .equ 0x0033
__prl3 .res.b 2 ;000034
PRL3 .equ 0x0034
.org 0x0034
__prll3 .res.b 1 ;000034
PRLL3 .equ 0x0034
__prlh3 .res.b 1 ;000035
PRLH3 .equ 0x0035
__prl45 .res.b 4 ;000036
PRL45 .equ 0x0036
.org 0x0036
__prl4 .res.b 2 ;000036
PRL4 .equ 0x0036
.org 0x0036
__prll4 .res.b 1 ;000036
PRLL4 .equ 0x0036
__prlh4 .res.b 1 ;000037
PRLH4 .equ 0x0037
__prl5 .res.b 2 ;000038
PRL5 .equ 0x0038
.org 0x0038
__prll5 .res.b 1 ;000038
PRLL5 .equ 0x0038
__prlh5 .res.b 1 ;000039
PRLH5 .equ 0x0039
__ppgc01 .res.b 2 ;00003A
PPGC01 .equ 0x003A
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