📄 mb90440.asm
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 28/01/03 TIME: 2:20:16 PM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or */
/* see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 09-04-01 1.0 HWE initial version */
/* 22.07.02 1.1 HWE new adc_01.h, icr.h (RMW-Problem) */
/* 28.01.03 1.2 HWE wordaccess to PPGCx/y: PPGC01, .. , PPGC67 */
/* 28.01.03 1.2 HWE wordaccess to PPG Reload: PRL1, .. , PRL7 */
/* 28.01.03 1.2 HWE longwordaccess to PPG Reload: PRL01, .. , PRL67 */
/* */
.PROGRAM MB90440
.TITLE MB90440
;------------------------
; IO-AREA DEFINITIONS :
;------------------------
.section IOBASE, IO, locate=0x0000 ; /* PORT DATA */
.GLOBAL __pdr0, __pdr1, __pdr2, __pdr3, __pdr4, __pdr5
.GLOBAL __pdr6, __pdr7, __pdr8, __pdr9, __pdra, __pilr
.GLOBAL __ddr0, __ddr1, __ddr2, __ddr3, __ddr4, __ddr5
.GLOBAL __ddr6, __ddr7, __ddr8, __ddr9, __ddra, __ader
.GLOBAL __pucr0, __pucr1, __pucr2, __pucr3, __umc0, __usr0
.GLOBAL __uidr0, __uodr0, __urd0, __smr1, __scr1, __sidr1
.GLOBAL __sodr1, __ssr1, __u1cdcr, __ses1, __scdcr, __smcs
.GLOBAL __sdr, __ses2, __enir, __eirr, __elvr, __adcs
.GLOBAL __adcs0, __adcs1, __adcr, __adcr0, __adcr1, __ppgc01
.GLOBAL __ppgc0, __ppgc1, __ppg01, __ppgc23, __ppgc2, __ppgc3
.GLOBAL __ppg23, __ppgc45, __ppgc4, __ppgc5, __ppg45, __ppgc67
.GLOBAL __ppgc6, __ppgc7, __ppg67, __ics01, __ics23, __ics45
.GLOBAL __ics67, __tmcsr0, __tmr0, __tmrlr0, __tmcsr1, __tmr1
.GLOBAL __tmrlr1, __ocs0, __ocs1, __ocs2, __ocs3, __canl2
.GLOBAL __tcdt, __tccs, __romm, __canl0, __canl1, __pacsr
.GLOBAL __dirr, __lpmcr, __ckscr, __arsr, __hacr, __ecsr
.GLOBAL __wdtc, __tbtc, __wtc, __fmcs, __icr
__pdr0 .res.b 1 ;000000 /* PORT DATA */
PDR0 .equ 0x0000
__pdr1 .res.b 1 ;000001
PDR1 .equ 0x0001
__pdr2 .res.b 1 ;000002
PDR2 .equ 0x0002
__pdr3 .res.b 1 ;000003
PDR3 .equ 0x0003
__pdr4 .res.b 1 ;000004
PDR4 .equ 0x0004
__pdr5 .res.b 1 ;000005
PDR5 .equ 0x0005
__pdr6 .res.b 1 ;000006
PDR6 .equ 0x0006
__pdr7 .res.b 1 ;000007
PDR7 .equ 0x0007
__pdr8 .res.b 1 ;000008
PDR8 .equ 0x0008
__pdr9 .res.b 1 ;000009
PDR9 .equ 0x0009
__pdra .res.b 1 ;00000A
PDRA .equ 0x000A
__pilr .res.b 1 ;00000B
PILR .equ 0x000B
.org 0x0010
__ddr0 .res.b 1 ;000010 /* PORT DIRECTION */
DDR0 .equ 0x0010
__ddr1 .res.b 1 ;000011
DDR1 .equ 0x0011
__ddr2 .res.b 1 ;000012
DDR2 .equ 0x0012
__ddr3 .res.b 1 ;000013
DDR3 .equ 0x0013
__ddr4 .res.b 1 ;000014
DDR4 .equ 0x0014
__ddr5 .res.b 1 ;000015
DDR5 .equ 0x0015
__ddr6 .res.b 1 ;000016
DDR6 .equ 0x0016
__ddr7 .res.b 1 ;000017
DDR7 .equ 0x0017
__ddr8 .res.b 1 ;000018
DDR8 .equ 0x0018
__ddr9 .res.b 1 ;000019
DDR9 .equ 0x0019
__ddra .res.b 1 ;00001A
DDRA .equ 0x001A
__ader .res.b 1 ;00001B
ADER .equ 0x001B
__pucr0 .res.b 1 ;00001C /* PULL-UP CONTROL */
PUCR0 .equ 0x001C
__pucr1 .res.b 1 ;00001D
PUCR1 .equ 0x001D
__pucr2 .res.b 1 ;00001E
PUCR2 .equ 0x001E
__pucr3 .res.b 1 ;00001F
PUCR3 .equ 0x001F
__umc0 .res.b 1 ;000020 /* UART0 */
UMC0 .equ 0x0020
__usr0 .res.b 1 ;000021
USR0 .equ 0x0021
__uidr0 .res.b 1 ;000022
UIDR0 .equ 0x0022
.org 0x0022
__uodr0 .res.b 1 ;000022
UODR0 .equ 0x0022
__urd0 .res.b 1 ;000023
URD0 .equ 0x0023
__smr1 .res.b 1 ;000024 /* UART1 SCI with clock selection */
SMR1 .equ 0x0024
__scr1 .res.b 1 ;000025
SCR1 .equ 0x0025
__sidr1 .res.b 1 ;000026
SIDR1 .equ 0x0026
.org 0x0026
__sodr1 .res.b 1 ;000026
SODR1 .equ 0x0026
__ssr1 .res.b 1 ;000027
SSR1 .equ 0x0027
__u1cdcr .res.b 1 ;000028
U1CDCR .equ 0x0028
__ses1 .res.b 1 ;000029
SES1 .equ 0x0029
.org 0x002B
__scdcr .res.b 1 ;00002B /* SIO with clock selection */
SCDCR .equ 0x002B
__smcs .res.b 2 ;00002C
SMCS .equ 0x002C
__sdr .res.b 1 ;00002E
SDR .equ 0x002E
__ses2 .res.b 1 ;00002F
SES2 .equ 0x002F
__enir .res.b 1 ;000030 /* DTP, External Interrupts */
ENIR .equ 0x0030
__eirr .res.b 1 ;000031
EIRR .equ 0x0031
__elvr .res.b 2 ;000032
ELVR .equ 0x0032
__adcs .res.b 2 ;000034 /* AD Converter */
ADCS .equ 0x0034
.org 0x0034
__adcs0 .res.b 1 ;000034
ADCS0 .equ 0x0034
__adcs1 .res.b 1 ;000035
ADCS1 .equ 0x0035
__adcr .res.b 2 ;000036
ADCR .equ 0x0036
.org 0x0036
__adcr0 .res.b 1 ;000036
ADCR0 .equ 0x0036
__adcr1 .res.b 1 ;000037
ADCR1 .equ 0x0037
__ppgc01 .res.b 2 ;000038 /* PPG control */
PPGC01 .equ 0x0038
.org 0x0038
__ppgc0 .res.b 1 ;000038
PPGC0 .equ 0x0038
__ppgc1 .res.b 1 ;000039
PPGC1 .equ 0x0039
__ppg01 .res.b 1 ;00003A
PPG01 .equ 0x003A
.org 0x003C
__ppgc23 .res.b 2 ;00003C
PPGC23 .equ 0x003C
.org 0x003C
__ppgc2 .res.b 1 ;00003C
PPGC2 .equ 0x003C
__ppgc3 .res.b 1 ;00003D
PPGC3 .equ 0x003D
__ppg23 .res.b 1 ;00003E
PPG23 .equ 0x003E
.org 0x0040
__ppgc45 .res.b 2 ;000040
PPGC45 .equ 0x0040
.org 0x0040
__ppgc4 .res.b 1 ;000040
PPGC4 .equ 0x0040
__ppgc5 .res.b 1 ;000041
PPGC5 .equ 0x0041
__ppg45 .res.b 1 ;000042
PPG45 .equ 0x0042
.org 0x0044
__ppgc67 .res.b 2 ;000044
PPGC67 .equ 0x0044
.org 0x0044
__ppgc6 .res.b 1 ;000044
PPGC6 .equ 0x0044
__ppgc7 .res.b 1 ;000045
PPGC7 .equ 0x0045
__ppg67 .res.b 1 ;000046
PPG67 .equ 0x0046
.org 0x004C
__ics01 .res.b 1 ;00004C
ICS01 .equ 0x004C
__ics23 .res.b 1 ;00004D
ICS23 .equ 0x004D
__ics45 .res.b 1 ;00004E
ICS45 .equ 0x004E
__ics67 .res.b 1 ;00004F
ICS67 .equ 0x004F
__tmcsr0 .res.b 2 ;000050
TMCSR0 .equ 0x0050
__tmr0 .res.b 2 ;000052
TMR0 .equ 0x0052
.org 0x0052
__tmrlr0 .res.b 2 ;000052
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