📄 mb90495.h
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/* FFMC-16 IO-MAP HEADER FILE */
/* ========================== */
/* SOFTUNE WORKBENCH FORMAT */
/* C-DEFINITIONS FOR IO-SYMBOLS */
/* CREATED BY IO-WIZARD V2.10 */
/* DATE: 27/01/03 TIME: 12:36:15 PM */
/* *********************************************************** */
/* FUJITSU MIKROELEKTRONIK GMBH */
/* Am Siebenstein 6-10, 63303 Dreieich */
/* Tel.:++49/6103/690-0,Fax - 122 */
/* */
/* The following software is for demonstration purposes only. */
/* It is not fully tested, nor validated in order to fullfill */
/* its task under all circumstances. Therefore, this software */
/* or any part of it must only be used in an evaluation */
/* laboratory environment. */
/* This software is subject to the rules of our standard */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD */
/* or see our Internet Page - */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html) */
/* *********************************************************** */
/* History: */
/* Date Version Author Description */
/* 21.10.99 1.0 VSA created */
/* 16.11.99 1.1 VSA ... */
/* 17.11.99 1.2 VSA ... */
/* 18.11.99 1.3 WP Rom Mirror + WTC added + O>0 at PPG */
/* 29.11.99 1.4 WP IPCP2+3 added UART1 register SMC1 > SMR1 */
/* 08.02.00 2.0 HLO added: !D to canh, canm was missing */
/* canmac.h, canstr.h -> canmac8.h, canstr.h */
/* 09.02.00 2.1 HLO CANSTR8.H updated */
/* 13.04.00 2.2 VSA TCCSH, TCCSL added */
/* 18.05.00 2.3 VSA write-only bits verified */
/* 03.07.00 2.4 VSA ADC unit included (adc_01.h) */
/* 10.08.00 2.5 HLO CANHSTR changed, wrong alignment of AMR */
/* 11.10.00 2.6 MST missing CLK2 bit in TCCS Register (IOTimer) added */
/* 27.10.00 2.7 NMP ADCS RESV bit location corrected */
/* PPGn Control Register bit description completed */
/* 16bit timer TCCSH_ECKE description corrected from FRCK */
/* SCR0 and SCR1 bit descriptions added */
/* 08.11.00 2.8 NMP Register bit TCCS_ICLR corrected */
/* 22.02.01 2.9 NMP Register bit TCCS bit corrected */
/* 28.03.01 2.10 TKA Section IOXTND splitted into IOXTND and IOXTND2 because of area in case of external bus used */
/* 11.04.01 2.11 HWE UART1: SMR1 UPCL Bit added */
/* UART1: SCR1 REC Bit added */
/* UART1: SSR1 BDS Bit added */
/* UART0: SCR0 REC Bit added */
/* 10.12.01 2.12 HWE TCCS: Bit ECKE added */
/* 23.07.02 2.13 HWe new adc_01.h, icr.h (RMW-Problem) */
/* 19.08.02 2.14 HWE Bitdefinition PPGC1/3 corrected (MD0, MD1) */
/* 27.01.03 2.15 HWE wordaccess to PPGCx/y: PPGC01, PPGC23 */
/* 27.01.03 2.15 HWE longwordaccess to PPG Reload: PRL01, PRL23 */
#ifndef __MB90XXX_H
# define __MB90XXX_H
/*
- Please define __IO_NEAR in LARGE and COMPACT memory model, if the default
data bank (DTB) is 00. This will result in better performance in these
models.
- Please define __IO_FAR in SMALL and MEDIUM memory model, if the default
data bank (DTB) is other than 00. This might be the case in systems with
external RAM, which are not using internal RAM as default data area.
- Please define neither __IO_NEAR nor __IO_FAR in all other cases. This
will work with almost all configurations.
*/
# ifdef __IO_NEAR
# ifdef __IO_FAR
# error __IO_NEAR and __IO_FAR must not be defined at the same time
# else
# define ___IOWIDTH __near
# endif
# else
# ifdef __IO_FAR
# define ___IOWIDTH __far
# else /* specified by memory model */
# define ___IOWIDTH
# endif
# endif
# ifdef __IO_DEFINE
# define __IO_EXTERN
# define __IO_EXTENDED volatile ___IOWIDTH
# else
# define __IO_EXTERN extern /* for data, which can have __io */
# define __IO_EXTENDED extern volatile ___IOWIDTH
# endif
typedef unsigned char IO_BYTE;
typedef unsigned short IO_WORD;
typedef unsigned long IO_LWORD;
typedef const unsigned short IO_WORD_READ;
/* REGISTER BIT STRUCTURES */
typedef union{ /* PORT DATA Registers */
IO_BYTE byte;
struct{
IO_BYTE P00 :1;
IO_BYTE P01 :1;
IO_BYTE P02 :1;
IO_BYTE P03 :1;
IO_BYTE P04 :1;
IO_BYTE P05 :1;
IO_BYTE P06 :1;
IO_BYTE P07 :1;
}bit;
}PDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P10 :1;
IO_BYTE P11 :1;
IO_BYTE P12 :1;
IO_BYTE P13 :1;
IO_BYTE P14 :1;
IO_BYTE P15 :1;
IO_BYTE P16 :1;
IO_BYTE P17 :1;
}bit;
}PDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P20 :1;
IO_BYTE P21 :1;
IO_BYTE P22 :1;
IO_BYTE P23 :1;
IO_BYTE P24 :1;
IO_BYTE P25 :1;
IO_BYTE P26 :1;
IO_BYTE P27 :1;
}bit;
}PDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P30 :1;
IO_BYTE P31 :1;
IO_BYTE P32 :1;
IO_BYTE P33 :1;
IO_BYTE P34 :1;
IO_BYTE P35 :1;
IO_BYTE P36 :1;
IO_BYTE P37 :1;
}bit;
}PDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P40 :1;
IO_BYTE P41 :1;
IO_BYTE P42 :1;
IO_BYTE P43 :1;
IO_BYTE P44 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}PDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P50 :1;
IO_BYTE P51 :1;
IO_BYTE P52 :1;
IO_BYTE P53 :1;
IO_BYTE P54 :1;
IO_BYTE P55 :1;
IO_BYTE P56 :1;
IO_BYTE P57 :1;
}bit;
}PDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE P60 :1;
IO_BYTE P61 :1;
IO_BYTE P62 :1;
IO_BYTE P63 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}PDR6STR;
typedef union{ /* PORT DIR */
IO_BYTE byte;
struct{
IO_BYTE D00 :1;
IO_BYTE D01 :1;
IO_BYTE D02 :1;
IO_BYTE D03 :1;
IO_BYTE D04 :1;
IO_BYTE D05 :1;
IO_BYTE D06 :1;
IO_BYTE D07 :1;
}bit;
}DDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D10 :1;
IO_BYTE D11 :1;
IO_BYTE D12 :1;
IO_BYTE D13 :1;
IO_BYTE D14 :1;
IO_BYTE D15 :1;
IO_BYTE D16 :1;
IO_BYTE D17 :1;
}bit;
}DDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D20 :1;
IO_BYTE D21 :1;
IO_BYTE D22 :1;
IO_BYTE D23 :1;
IO_BYTE D24 :1;
IO_BYTE D25 :1;
IO_BYTE D26 :1;
IO_BYTE D27 :1;
}bit;
}DDR2STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D30 :1;
IO_BYTE D31 :1;
IO_BYTE D32 :1;
IO_BYTE D33 :1;
IO_BYTE D34 :1;
IO_BYTE D35 :1;
IO_BYTE D36 :1;
IO_BYTE D37 :1;
}bit;
}DDR3STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D40 :1;
IO_BYTE D41 :1;
IO_BYTE D42 :1;
IO_BYTE D43 :1;
IO_BYTE D44 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}DDR4STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D50 :1;
IO_BYTE D51 :1;
IO_BYTE D52 :1;
IO_BYTE D53 :1;
IO_BYTE D54 :1;
IO_BYTE D55 :1;
IO_BYTE D56 :1;
IO_BYTE D57 :1;
}bit;
}DDR5STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D60 :1;
IO_BYTE D61 :1;
IO_BYTE D62 :1;
IO_BYTE D63 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}DDR6STR;
typedef union{ /* AnalogInputEnable Port 5 */
IO_BYTE byte;
struct{
IO_BYTE ADE0 :1;
IO_BYTE ADE1 :1;
IO_BYTE ADE2 :1;
IO_BYTE ADE3 :1;
IO_BYTE ADE4 :1;
IO_BYTE ADE5 :1;
IO_BYTE ADE6 :1;
IO_BYTE ADE7 :1;
}bit;
}ADERSTR;
typedef union{ /* UART0 */
IO_BYTE byte;
struct{
IO_BYTE SOE :1;
IO_BYTE SCKE :1;
IO_BYTE :1;
IO_BYTE CS0 :1;
IO_BYTE CS1 :1;
IO_BYTE CS2 :1;
IO_BYTE MD0 :1;
IO_BYTE MD1 :1;
}bit;
struct{
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE CS :3;
IO_BYTE MD :2;
}bitc;
}SMR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TXE :1;
IO_BYTE RXE :1;
IO_BYTE REC :1;
IO_BYTE AD :1;
IO_BYTE CL :1;
IO_BYTE SBL :1;
IO_BYTE P :1;
IO_BYTE PEN :1;
}bit;
}SCR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SIDR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SODR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TIE :1;
IO_BYTE RIE :1;
IO_BYTE :1;
IO_BYTE TDRE :1;
IO_BYTE RDRF :1;
IO_BYTE FRE :1;
IO_BYTE ORE :1;
IO_BYTE PE :1;
}bit;
}SSR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE DIV0 :1;
IO_BYTE DIV1 :1;
IO_BYTE DIV2 :1;
IO_BYTE DIV3 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE MD :1;
}bit;
struct{
IO_BYTE DIV :4;
}bitc;
}CDCR0STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE NEG :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
}bit;
}SES0STR;
typedef union{ /* UART1 */
IO_BYTE byte;
struct{
IO_BYTE SOE :1;
IO_BYTE SCKE :1;
IO_BYTE UPCL :1;
IO_BYTE CS0 :1;
IO_BYTE CS1 :1;
IO_BYTE CS2 :1;
IO_BYTE MD0 :1;
IO_BYTE MD1 :1;
}bit;
struct{
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE CS :3;
IO_BYTE MD :2;
}bitc;
}SMR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TXE :1;
IO_BYTE RXE :1;
IO_BYTE REC :1;
IO_BYTE AD :1;
IO_BYTE CL :1;
IO_BYTE SBL :1;
IO_BYTE P :1;
IO_BYTE PEN :1;
}bit;
}SCR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SIDR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE D0 :1;
IO_BYTE D1 :1;
IO_BYTE D2 :1;
IO_BYTE D3 :1;
IO_BYTE D4 :1;
IO_BYTE D5 :1;
IO_BYTE D6 :1;
IO_BYTE D7 :1;
}bit;
}SODR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE TIE :1;
IO_BYTE RIE :1;
IO_BYTE BDS :1;
IO_BYTE TDRE :1;
IO_BYTE RDRF :1;
IO_BYTE FRE :1;
IO_BYTE ORE :1;
IO_BYTE PE :1;
}bit;
}SSR1STR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE DIV0 :1;
IO_BYTE DIV1 :1;
IO_BYTE DIV2 :1;
IO_BYTE DIV3 :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE :1;
IO_BYTE MD :1;
}bit;
struct{
IO_BYTE DIV :4;
}bitc;
}CDCR1STR;
typedef union{ /* DTP, External Interrupts */
IO_BYTE byte;
struct{
IO_BYTE EN0 :1;
IO_BYTE EN1 :1;
IO_BYTE EN2 :1;
IO_BYTE EN3 :1;
IO_BYTE EN4 :1;
IO_BYTE EN5 :1;
IO_BYTE EN6 :1;
IO_BYTE EN7 :1;
}bit;
}ENIRSTR;
typedef union{
IO_BYTE byte;
struct{
IO_BYTE ER0 :1;
IO_BYTE ER1 :1;
IO_BYTE ER2 :1;
IO_BYTE ER3 :1;
IO_BYTE ER4 :1;
IO_BYTE ER5 :1;
IO_BYTE ER6 :1;
IO_BYTE ER7 :1;
}bit;
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