mb90540.asm

富士通单片机MB90F387上实现MODBUS

/*  FFMC-16 IO-MAP HEADER FILE      */
/*  ==========================      */
/* CREATED BY IO-WIZARD V2.10   */
/* DATE: 29/01/03 TIME: 1:30:38 PM */
/* *********************************************************** */
/*               FUJITSU MIKROELEKTRONIK GMBH                  */
/*               Am Siebenstein 6-10, 63303 Dreieich           */
/*               Tel.:++49/6103/690-0,Fax - 122                */
/*                                                             */
/* The following software is for demonstration purposes only.  */
/* It is not fully tested, nor validated in order to fullfill  */
/* its task under all circumstances. Therefore, this software  */
/* or any part of it must only be used in an evaluation        */
/* laboratory environment.                                     */
/* This software is subject to the rules of our standard       */
/* DISCLAIMER, that is delivered with our SW-tools (on the CD  */
/* "Micros Documentation & Software V3.0" see "\START.HTM" or  */
/* see our Internet Page -                                     */
/* http://www.fujitsu-ede.com/products/micro/disclaimer.html   */
/* *********************************************************** */
/* History: */
/* Date      Version     Author      Description */
/* 01-12-98  1.0 initial version */
/*           wtc: bitgroup removed because of same name as byte macro */
/*  */
/* 23-01-99  2.0 */
/* 	- CAN includes changed (structures for whole area) */
/* 	- SMR0 (mistake) changed to SMR1 */
/* 03-02-99  2.1    */
/* 	- LWORD macros and identifier changed to DWORD */
/* 	- ICR resource used as include */
/* 	- CAN includes statements splitted (successive statements are ignored with old version) */
/* 14.04.99  2.2	JRO */
/* 	- generation of header and c file with IO-Wizard V 1.9 */
/*  */
/* 29.04.99  2.3	VSA */
/* 	- bitdefinitions for parallelports are changed to Pxx, Dxx */
/* 30.04.99  2.4	VSA */
/* 	- 3903h PRHL1 -> PRLH1 */
/* 	- 3907h PRHL3 -> PRLH3 */
/* 	- 390Bh PRHL5 -> PRLH5 */
/* 	- 390Fh PRHL7 -> PRLH7 */
/* 	- 1FF0h: PADR0 3 (3 byte array) */
/* 	- 1FF3h: PADR1 3 (3 byte array) */
/* 	- PADR2, PADR3, PADR4, PADR5 are deleted */
/* 	- address of SCDCR from 2Ah to 2Bh changed */
/* 	- ADCS1 -> ADCS0 */
/* 	- ADCS2 -> ADCS1 */
/* 	- ADCR1 -> ADCR0 */
/* 	- ADCR2 -> ADCR1 */
/* 	- ARSR, HACR, ECSR are deleted */
/* 	- address of OCCP1 are from 3929h to 392Ah changed */
/* 	-    -    -  OCCP2  -  from 392Ah to 392Ch    - */
/* 	-    -    -  OCCP3  -  from 392Bh to 392Eh    - */
/* 07.05.99 2.5    	VSA */
/* 	- disclaimer added                                   */
/* 15.07.99 2.6		VSA */
/* 	- _elvr is changed to elvr */
/* 	- _canlx are changed to canlx */
/* 	- PADRx 3 are renamed to PADRx_L 1, PADRx_M 1, PADRx_H 1 */
/* 16.08.99 2.7		VSA */
/* 	- ARSR, HACR, ECSR are inserted */
/* 23.08.99 2.8		VSA */
/* 	- SMCS bitdefinitions modified */
/* 	- security section added */
/* 03.07.00 2.9 	VSA */
/* 	- ADC unit included (adc_01.h) */
/* 27.10.00 3.0         NMP */
/*              - ADC Macro ammended */
/* 08.11.00 3.1 - Rebuild to remove incorrect comments */
/* 16.03.01 3.4  */
/*           - Updated ADC Macro, RESV bit in ADCS1 added  */
/* 28.03.01 3.5    TKA      Section IOXTND splitted into IOXTND and IOXTND2 because of area in case of external bus used */
/* 23.07.02 3.6    HWe      new adc_01.h, icr.h (RMW-Problem) */
/* 29.01.03 3.7    HWE      wordaccess to PPGCx/y: PPGC01, .. , PPGC67 */
/* 29.01.03 3.7    HWE      wordaccess to PPG Reload: PRL0, .. , PRL7 */
/* 29.01.03 3.7    HWE      longwordaccess to PPG Reload: PRL01, .. , PRL67 */

 .PROGRAM MB90540
 .TITLE   MB90540

;------------------------
; IO-AREA DEFINITIONS :
;------------------------



 .section IOBASE, IO, locate=0x0000  ; /*  PORT DATA */
 .GLOBAL __pdr0,     __pdr1,     __pdr2,     __pdr3,     __pdr4,     __pdr5
 .GLOBAL __pdr6,     __pdr7,     __pdr8,     __pdr9,     __pdra,     __ddr0
 .GLOBAL __ddr1,     __ddr2,     __ddr3,     __ddr4,     __ddr5,     __ddr6
 .GLOBAL __ddr7,     __ddr8,     __ddr9,     __ddra,     __ader,     __pucr0
 .GLOBAL __pucr1,    __pucr2,    __pucr3,    __umc0,     __usr0,     __uidr0
 .GLOBAL __uodr0,    __urd0,     __smr1,     __scr1,     __sidr1,    __sodr1
 .GLOBAL __ssr1,     __u1cdcr,   __ses1,     __scdcr,    __smcs,     __sdr
 .GLOBAL __ses2,     __enir,     __eirr,     __elvr,     __adcs,     __adcs0
 .GLOBAL __adcs1,    __adcr,     __adcr0,    __adcr1,    __ppgc01,   __ppgc0
 .GLOBAL __ppgc1,    __ppg01,    __ppgc23,   __ppgc2,    __ppgc3,    __ppg23
 .GLOBAL __ppgc45,   __ppgc4,    __ppgc5,    __ppg45,    __ppgc67,   __ppgc6
 .GLOBAL __ppgc7,    __ppg67,    __ics01,    __ics23,    __ics45,    __ics67
 .GLOBAL __tmcsr0,   __tmr0,     __tmrlr0,   __tmcsr1,   __tmr1,     __tmrlr1
 .GLOBAL __ocs0,     __ocs1,     __ocs2,     __ocs3,     __tcdt,     __tccs
 .GLOBAL __romm,     __canl0,    __canl1,    __pacsr,    __dirr,     __lpmcr
 .GLOBAL __ckscr,    __arsr,     __hacr,     __ecsr,     __wdtc,     __tbtc
 .GLOBAL __wtc,      __fmcs,     __icr

__pdr0   .res.b 1             ;000000  /*  PORT DATA */
PDR0    .equ 0x0000
__pdr1   .res.b 1             ;000001
PDR1    .equ 0x0001
__pdr2   .res.b 1             ;000002
PDR2    .equ 0x0002
__pdr3   .res.b 1             ;000003
PDR3    .equ 0x0003
__pdr4   .res.b 1             ;000004
PDR4    .equ 0x0004
__pdr5   .res.b 1             ;000005
PDR5    .equ 0x0005
__pdr6   .res.b 1             ;000006
PDR6    .equ 0x0006
__pdr7   .res.b 1             ;000007
PDR7    .equ 0x0007
__pdr8   .res.b 1             ;000008
PDR8    .equ 0x0008
__pdr9   .res.b 1             ;000009
PDR9    .equ 0x0009
__pdra   .res.b 1             ;00000A
PDRA    .equ 0x000A
 .org 0x0010
__ddr0   .res.b 1             ;000010  /*  PORT DIRECTION */
DDR0    .equ 0x0010
__ddr1   .res.b 1             ;000011
DDR1    .equ 0x0011
__ddr2   .res.b 1             ;000012
DDR2    .equ 0x0012
__ddr3   .res.b 1             ;000013
DDR3    .equ 0x0013
__ddr4   .res.b 1             ;000014
DDR4    .equ 0x0014
__ddr5   .res.b 1             ;000015
DDR5    .equ 0x0015
__ddr6   .res.b 1             ;000016
DDR6    .equ 0x0016
__ddr7   .res.b 1             ;000017
DDR7    .equ 0x0017
__ddr8   .res.b 1             ;000018
DDR8    .equ 0x0018
__ddr9   .res.b 1             ;000019
DDR9    .equ 0x0019
__ddra   .res.b 1             ;00001A
DDRA    .equ 0x001A
__ader   .res.b 1             ;00001B
ADER    .equ 0x001B
__pucr0   .res.b 1             ;00001C  /*  PULL-UP CONTROL */
PUCR0    .equ 0x001C
__pucr1   .res.b 1             ;00001D
PUCR1    .equ 0x001D
__pucr2   .res.b 1             ;00001E
PUCR2    .equ 0x001E
__pucr3   .res.b 1             ;00001F
PUCR3    .equ 0x001F
__umc0   .res.b 1             ;000020  /*  UART0 */
UMC0    .equ 0x0020
__usr0   .res.b 1             ;000021
USR0    .equ 0x0021
__uidr0   .res.b 1             ;000022
UIDR0    .equ 0x0022
 .org 0x0022
__uodr0   .res.b 1             ;000022
UODR0    .equ 0x0022
__urd0   .res.b 1             ;000023
URD0    .equ 0x0023
__smr1   .res.b 1             ;000024  /*  UART1 SCI with clock selection */
SMR1    .equ 0x0024
__scr1   .res.b 1             ;000025
SCR1    .equ 0x0025
__sidr1   .res.b 1             ;000026
SIDR1    .equ 0x0026
 .org 0x0026
__sodr1   .res.b 1             ;000026
SODR1    .equ 0x0026
__ssr1   .res.b 1             ;000027
SSR1    .equ 0x0027
__u1cdcr   .res.b 1             ;000028
U1CDCR    .equ 0x0028
__ses1   .res.b 1             ;000029
SES1    .equ 0x0029
 .org 0x002B
__scdcr   .res.b 1             ;00002B  /*  SIO with clock selection */
SCDCR    .equ 0x002B
__smcs   .res.b 2             ;00002C
SMCS    .equ 0x002C
__sdr   .res.b 1             ;00002E
SDR    .equ 0x002E
__ses2   .res.b 1             ;00002F
SES2    .equ 0x002F
__enir   .res.b 1             ;000030  /*  DTP, External Interrupts */
ENIR    .equ 0x0030
__eirr   .res.b 1             ;000031
EIRR    .equ 0x0031
__elvr   .res.b 2             ;000032
ELVR    .equ 0x0032
__adcs   .res.b 2             ;000034  /* AD Converter */
ADCS    .equ 0x0034
 .org 0x0034
__adcs0   .res.b 1             ;000034
ADCS0    .equ 0x0034
__adcs1   .res.b 1             ;000035
ADCS1    .equ 0x0035
__adcr   .res.b 2             ;000036
ADCR    .equ 0x0036
 .org 0x0036
__adcr0   .res.b 1             ;000036
ADCR0    .equ 0x0036
__adcr1   .res.b 1             ;000037
ADCR1    .equ 0x0037
__ppgc01   .res.b 2             ;000038  /*  PPG control */
PPGC01    .equ 0x0038
 .org 0x0038
__ppgc0   .res.b 1             ;000038
PPGC0    .equ 0x0038
__ppgc1   .res.b 1             ;000039
PPGC1    .equ 0x0039
__ppg01   .res.b 1             ;00003A
PPG01    .equ 0x003A
 .org 0x003C
__ppgc23   .res.b 2             ;00003C
PPGC23    .equ 0x003C
 .org 0x003C
__ppgc2   .res.b 1             ;00003C
PPGC2    .equ 0x003C
__ppgc3   .res.b 1             ;00003D
PPGC3    .equ 0x003D
__ppg23   .res.b 1             ;00003E
PPG23    .equ 0x003E
 .org 0x0040
__ppgc45   .res.b 2             ;000040
PPGC45    .equ 0x0040
 .org 0x0040
__ppgc4   .res.b 1             ;000040