make.html

Linux下Makefile的编写手册。全部是中文版

prerequisites, the source file and header files.  This makefile does not
specify anything to be done for them&mdash;the `<samp><span class="samp">.c</span></samp>' and `<samp><span class="samp">.h</span></samp>' files
are not the targets of any rules&mdash;so <code>make</code> does nothing for these
files.  But <code>make</code> would update automatically generated C programs,
such as those made by Bison or Yacc, by their own rules at this time.

   <p>After recompiling whichever object files need it, <code>make</code> decides
whether to relink <samp><span class="file">edit</span></samp>.  This must be done if the file
<samp><span class="file">edit</span></samp> does not exist, or if any of the object files are newer than
it.  If an object file was just recompiled, it is now newer than
<samp><span class="file">edit</span></samp>, so <samp><span class="file">edit</span></samp> is relinked. 
<a name="index-relinking-32"></a>
Thus, if we change the file <samp><span class="file">insert.c</span></samp> and run <code>make</code>,
<code>make</code> will compile that file to update <samp><span class="file">insert.o</span></samp>, and then
link <samp><span class="file">edit</span></samp>.  If we change the file <samp><span class="file">command.h</span></samp> and run
<code>make</code>, <code>make</code> will recompile the object files <samp><span class="file">kbd.o</span></samp>,
<samp><span class="file">command.o</span></samp> and <samp><span class="file">files.o</span></samp> and then link the file <samp><span class="file">edit</span></samp>.

<div class="node">
<p><hr>
<a name="Variables-Simplify"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="#make-Deduces">make Deduces</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="#How-Make-Works">How Make Works</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="#Introduction">Introduction</a>

</div>

<h3 class="section">2.4 Variables Make Makefiles Simpler</h3>

<p><a name="index-variables-33"></a><a name="index-simplifying-with-variables-34"></a>
In our example, we had to list all the object files twice in the rule for
<samp><span class="file">edit</span></samp> (repeated here):

<pre class="example">     edit : main.o kbd.o command.o display.o \
                   insert.o search.o files.o utils.o
             cc -o edit main.o kbd.o command.o display.o \
                        insert.o search.o files.o utils.o
</pre>
   <p><a name="index-g_t_0040code_007bobjects_007d-35"></a>Such duplication is error-prone; if a new object file is added to the
system, we might add it to one list and forget the other.  We can eliminate
the risk and simplify the makefile by using a variable.  <dfn>Variables</dfn>
allow a text string to be defined once and substituted in multiple places
later (see <a href="#Using-Variables">How to Use Variables</a>).

   <p><a name="index-g_t_0040code_007bOBJECTS_007d-36"></a><a name="index-g_t_0040code_007bobjs_007d-37"></a><a name="index-g_t_0040code_007bOBJS_007d-38"></a><a name="index-g_t_0040code_007bobj_007d-39"></a><a name="index-g_t_0040code_007bOBJ_007d-40"></a>It is standard practice for every makefile to have a variable named
<code>objects</code>, <code>OBJECTS</code>, <code>objs</code>, <code>OBJS</code>, <code>obj</code>,
or <code>OBJ</code> which is a list of all object file names.  We would
define such a variable <code>objects</code> with a line like this in the
makefile:

<pre class="example">     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o
</pre>
   <p class="noindent">Then, each place we want to put a list of the object file names, we can
substitute the variable's value by writing `<samp><span class="samp">$(objects)</span></samp>'
(see <a href="#Using-Variables">How to Use Variables</a>).

   <p>Here is how the complete simple makefile looks when you use a variable
for the object files:

<pre class="example">     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o
     
     edit : $(objects)
             cc -o edit $(objects)
     main.o : main.c defs.h
             cc -c main.c
     kbd.o : kbd.c defs.h command.h
             cc -c kbd.c
     command.o : command.c defs.h command.h
             cc -c command.c
     display.o : display.c defs.h buffer.h
             cc -c display.c
     insert.o : insert.c defs.h buffer.h
             cc -c insert.c
     search.o : search.c defs.h buffer.h
             cc -c search.c
     files.o : files.c defs.h buffer.h command.h
             cc -c files.c
     utils.o : utils.c defs.h
             cc -c utils.c
     clean :
             rm edit $(objects)
</pre>
   <div class="node">
<p><hr>
<a name="make-Deduces"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="#Combine-By-Prerequisite">Combine By Prerequisite</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="#Variables-Simplify">Variables Simplify</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="#Introduction">Introduction</a>

</div>

<h3 class="section">2.5 Letting <code>make</code> Deduce the Commands</h3>

<p><a name="index-deducing-commands-_0028implicit-rules_0029-41"></a><a name="index-implicit-rule_002c-introduction-to-42"></a><a name="index-rule_002c-implicit_002c-introduction-to-43"></a>
It is not necessary to spell out the commands for compiling the individual
C source files, because <code>make</code> can figure them out: it has an
<dfn>implicit rule</dfn> for updating a `<samp><span class="samp">.o</span></samp>' file from a correspondingly
named `<samp><span class="samp">.c</span></samp>' file using a `<samp><span class="samp">cc -c</span></samp>' command.  For example, it will
use the command `<samp><span class="samp">cc -c main.c -o main.o</span></samp>' to compile <samp><span class="file">main.c</span></samp> into
<samp><span class="file">main.o</span></samp>.  We can therefore omit the commands from the rules for the
object files.  See <a href="#Implicit-Rules">Using Implicit Rules</a>.

   <p>When a `<samp><span class="samp">.c</span></samp>' file is used automatically in this way, it is also
automatically added to the list of prerequisites.  We can therefore omit
the `<samp><span class="samp">.c</span></samp>' files from the prerequisites, provided we omit the commands.

   <p>Here is the entire example, with both of these changes, and a variable
<code>objects</code> as suggested above:

<pre class="example">     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o
     
     edit : $(objects)
             cc -o edit $(objects)
     
     main.o : defs.h
     kbd.o : defs.h command.h
     command.o : defs.h command.h
     display.o : defs.h buffer.h
     insert.o : defs.h buffer.h
     search.o : defs.h buffer.h
     files.o : defs.h buffer.h command.h
     utils.o : defs.h
     
     .PHONY : clean
     clean :
             rm edit $(objects)
</pre>
   <p class="noindent">This is how we would write the makefile in actual practice.  (The
complications associated with `<samp><span class="samp">clean</span></samp>' are described elsewhere. 
See <a href="#Phony-Targets">Phony Targets</a>, and <a href="#Errors">Errors in Commands</a>.)

   <p>Because implicit rules are so convenient, they are important.  You
will see them used frequently.

<div class="node">
<p><hr>
<a name="Combine-By-Prerequisite"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="#Cleanup">Cleanup</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="#make-Deduces">make Deduces</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="#Introduction">Introduction</a>

</div>

<h3 class="section">2.6 Another Style of Makefile</h3>

<p><a name="index-combining-rules-by-prerequisite-44"></a>
When the objects of a makefile are created only by implicit rules, an
alternative style of makefile is possible.  In this style of makefile,
you group entries by their prerequisites instead of by their targets. 
Here is what one looks like:

<pre class="example">     objects = main.o kbd.o command.o display.o \
               insert.o search.o files.o utils.o
     
     edit : $(objects)
             cc -o edit $(objects)
     
     $(objects) : defs.h
     kbd.o command.o files.o : command.h
     display.o insert.o search.o files.o : buffer.h
</pre>
   <p class="noindent">Here <samp><span class="file">defs.h</span></samp> is given as a prerequisite of all the object files;
<samp><span class="file">command.h</span></samp> and <samp><span class="file">buffer.h</span></samp> are prerequisites of the specific
object files listed for them.

   <p>Whether this is better is a matter of taste: it is more compact, but some
people dislike it because they find it clearer to put all the information
about each target in one place.

<div class="node">
<p><hr>
<a name="Cleanup"></a>
Previous:&nbsp;<a rel="previous" accesskey="p" href="#Combine-By-Prerequisite">Combine By Prerequisite</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="#Introduction">Introduction</a>

</div>

<h3 class="section">2.7 Rules for Cleaning the Directory</h3>

<p><a name="index-cleaning-up-45"></a><a name="index-removing_002c-to-clean-up-46"></a>
Compiling a program is not the only thing you might want to write rules
for.  Makefiles commonly tell how to do a few other things besides
compiling a program: for example, how to delete all the object files
and executables so that the directory is `<samp><span class="samp">clean</span></samp>'.

   <p><a name="index-g_t_0040code_007bclean_007d-target-47"></a>Here is how we
could write a <code>make</code> rule for cleaning our example editor:

<pre class="example">     clean:
             rm edit $(objects)
</pre>
   <p>In practice, we might want to write the rule in a somewhat more
complicated manner to handle unanticipated situations.  We would do this:

<pre class="example">     .PHONY : clean
     clean :
             -rm edit $(objects)
</pre>
   <p class="noindent">This prevents <code>make</code> from getting confused by an actual file
called <samp><span class="file">clean</span></samp> and causes it to continue in spite of errors from
<code>rm</code>.  (See <a href="#Phony-Targets">Phony Targets</a>, and <a href="#Errors">Errors in Commands</a>.)

<p class="noindent">A rule such as this should not be placed at the beginning of the
makefile, because we do not want it to run by default!  Thus, in the
example makefile, we want the rule for <code>edit</code>, which recompiles
the editor, to remain the default goal.

   <p>Since <code>clean</code> is not a prerequisite of <code>edit</code>, this rule will not
run at all if we give the command `<samp><span class="samp">make</span></samp>' with no arguments.  In
order to make the rule run, we have to type `<samp><span class="samp">make clean</span></samp>'. 
See <a href="#Running">How to Run <code>make</code></a>.

<div class="node">
<p><hr>
<a name="Makefiles"></a>
Next:&nbsp;<a rel="next" accesskey="n" href="#Rules">Rules</a>,
Previous:&nbsp;<a rel="previous" accesskey="p" href="#Introduction">Introduction</a>,
Up:&nbsp;<a rel="up" accesskey="u" href="#Top">Top</a>

</div>

<h2 class="chapter">3 Writing Makefiles</h2>

<p><a name="index-makefile_002c-how-to-write-48"></a>The information that tells <code>make</code> how to recompile a system comes from
reading a data base called the <dfn>makefile</dfn>.

<ul class="menu">
<li><a accesskey="1" href="#Makefile-Contents">Makefile Contents</a>:            What makefiles contain. 
<li><a accesskey="2" href="#Makefile-Names">Makefile Names</a>:               How to name your makefile. 
<li><a accesskey="3" href="#Include">Include</a>:                      How one makefile can use another makefile. 
<li><a accesskey="4" href="#MAKEFILES-Variable">MAKEFILES Variable</a>:           The environment can specify extra makefiles. 
<li><a accesskey="5" href="#MAKEFILE_005fLIST-Variable">MAKEFILE_LIST Variable</a>:       Discover which makefiles have been read. 
<li><a accesskey="6" href="#Special-Variables">Special Variables</a>:            Other special variables. 
<li><a accesskey="7" href="#Remaking-Makefiles">Remaking Makefiles</a>:           How makefiles get remade. 
<li><a accesskey="8" href="#Overriding-Makefiles">Overriding Makefiles</a>:         How to override part of one makefile
                                  with another makefile. 
<li><a acc