📄 main.s54
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;******************************************************************************
; SJTU DSP Tech. Center
; Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
; History:
; Date Authors Changes
; 2003/08/30 Xu Sheng Created.
;******************************************************************************
.mmregs
;************************** DMA register address ******************************
DMPREC .set 0x54
DMSA .set 0x55
DMSDI .set 0x56
;******************************************************************************
;************************** CPLD register address *****************************
USER_REG .set 0
DC_REG .set 1
CODEC_L .set 2
CODEC_H .set 3
VERSION .set 4
DM_CNTL .set 5
MISC .set 6
CODEC_CLK .set 7
;******************************************************************************
;**************************constants*******************************************
DATA_STORE_SIZE .set 16
STACK_ADDR .set 0x0500 ;stack top pointer
;******************************************************************************
;************************memory allocation*************************************
;allocate two memory space: src_buf, dst_buf
.bss src_buf, DATA_STORE_SIZE
.bss dst_buf, DATA_STORE_SIZE
.bss tmp_var, 1
.bss dma0_int_flag, 1
;******************************************************************************
;**************************functions*******************************************
.global main
.global DSPInit
;******************************************************************************
.text
;******************************************************************************
;** Function: main
;** Description: Main program
;******************************************************************************
main:
stm #STACK_ADDR, SP
;DSP initialization (inluding settings of CPLD, DMA and McBSP )
call DSPInit
;LED0 shines to show that all initializations have finished
portr #USER_REG, *(tmp_var)
orm #0x0001, *(tmp_var)
portw *(tmp_var), #USER_REG
sub A ;clear acc A
;initialize src_buf
stm #src_buf, AR2
ld #1, B
stm #DATA_STORE_SIZE-1, BRC
rptb init_src_loop-1
stl A, *AR2+
add B, A
init_src_loop:
stm #0x4180, DMPREC ;DMPREC
;AUTOIX=1, each DMA channel use its own global reload registers
;DPRC[5..0]=000001, DMA channel 0 has high priority
;INTOSEL[1,0]=10, use DAM channel 1-3 interrupts
;DE[5..0]=000000, disable all DMA channels
;========================================
; use DMA 0 transfer, both src and dst are contiguous
; poll the register to know the end of the transfer
stm #DMA_CNST0, AR3
stm #0, DMSA
stm #DMSDI, AR2
rpt #62-1
mvdd *AR3+, *AR2
;enable DMA 0
orm #0x0001, *(DMPREC)
;ldm DMPREC, A
;or #0x0001, A
;stm A, DMPREC
poll_loop:
ldm DMPREC, A
and #0x0001, A
bc poll_loop, ANEQ
;bitf DMPREC, #0x0001
;bc poll_loop, TC
;========================================
; set DMA 0 transfer, src and dst are modified with different
; index, use interrupt to notify CPU
;ready for data receive
stm #0x0040, IMR ;set IMR to enable DMA0(bit 6) Interrupt
stm #0xFFFF, IFR ;set IFR to clear pending interrupt
stm #DMA_CNST1, AR3
stm #0, DMSA
stm #DMSDI, AR2
rpt #62-1
mvdd *AR3+, *AR2
;enable DMA 0
rsbx INTM ;enable all interrupts
orm #0x0001, *(DMPREC)
;wait for DMA transfer stop
st #0, *(dma0_int_flag)
wait_dma_loop:
ld *(dma0_int_flag), A
nop
nop
bc wait_dma_loop, AEQ
;DMA transferring complete
dead_loop:
nop
nop
nop
b dead_loop
;**************************vectors*********************************************
.sect "vectors"
int_reset:
b main ;Main program
nop
nop
.space 84*16
int_damc0:
orm #1, *(dma0_int_flag)
rete
.space 33*16
;============================================================
.sect "DMA_tst_table"
DMA_CNST0:
.word src_buf ;DMSRC0
.word dst_buf ;DMDST0
.word DATA_STORE_SIZE-1 ;DMCTR0
.word 0x0000 ;DMSFC0
;DSYN=0000, no synchronized event
;DBLW=0, single word mode
;FRMCNT=1-1
.word 0x0145 ;DMMCR0
;AUTOINIT=0, disable auto-initialization
;DINM=0, IMOD=0, mask off DMAC0 interrupt
;CTMOD=0, multi-frame mode
;SIND=001, source address modificaion: post-add 1
;DMS=01, data space
;DIND=001, destination address modification: post-add 1
;DMD=01, data space
.word 0 ;DMSRC1
.word 0 ;DMDST1
.word 0 ;DMCTR1
.word 0 ;DMSFC1
.word 0 ;DMMCR1
.word 0 ;DMSRC2
.word 0 ;DMDST2
.word 0 ;DMCTR2
.word 0 ;DMSFC2
.word 0 ;DMMCR2
.word 0 ;DMSRC3
.word 0 ;DMDST3
.word 0 ;DMCTR3
.word 0 ;DMSFC3
.word 0 ;DMMCR3
.word 0 ;DMSRC4
.word 0 ;DMDST4
.word 0 ;DMCTR4
.word 0 ;DMSFC4
.word 0 ;DMMCR4
.word 0 ;DMSRC5
.word 0 ;DMDST5
.word 0 ;DMCTR5
.word 0 ;DMSFC5
.word 0 ;DMMCR5
.word 0 ;DMSRCP, no extended addressing
.word 0 ;DMDSTP, no extended addressing
.word 0 ;DMIDX0
.word 0 ;DMIDX1
.word 0 ;DMFRI0
.word 0 ;DMFRI1
.word 0 ;DMGSA0
.word 0 ;DMGDA0
.word 0 ;DMGCR0
.word 0 ;DMGFR0
.word 0 ;XSRCDP
.word 0 ;XDSTDP
.word 0 ;DMGSA1
.word 0 ;DMGDA1
.word 0 ;DMGCR1
.word 0 ;DMGFR1
.word 0 ;DMGSA2
.word 0 ;DMGDA2
.word 0 ;DMGCR2
.word 0 ;DMGFR2
.word 0 ;DMGSA3
.word 0 ;DMGDA3
.word 0 ;DMGCR3
.word 0 ;DMGFR3
.word 0 ;DMGSA4
.word 0 ;DMGDA4
.word 0 ;DMGCR4
.word 0 ;DMGFR4
.word 0 ;DMGSA5
.word 0 ;DMGDA5
.word 0 ;DMGCR5
.word 0 ;DMGFR5
DMA_CNST1:
.word src_buf ;DMSRC0
.word dst_buf ;DMDST0
.word DATA_STORE_SIZE/4-1 ;DMCTR0
.word 0x0003 ;DMSFC0
;DSYN=0000, no synchronized event
;DBLW=0, single word mode
;FRMCNT=4-1
.word 0x4155 ;DMMCR0
;AUTOINIT=0,
;DINM=1, DMAC0 interrupt determined by IMOD
;IMOD=0, DMAC0 interrupted when complete one block transferring
;CTMOD=0, multi-frame mode
;SIND=001, source address modification: post-add 1
;DMS=01, source address is in data space
;DIND=101, destination address modification: determined by DMIDX0 & DMFRI0
;DMD=01, destination address is in data space
.word 0 ;DMSRC1
.word 0 ;DMDST1
.word 0 ;DMCTR1
.word 0 ;DMSFC1
.word 0 ;DMMCR1
.word 0 ;DMSRC2
.word 0 ;DMDST2
.word 0 ;DMCTR2
.word 0 ;DMSFC2
.word 0 ;DMMCR2
.word 0 ;DMSRC3
.word 0 ;DMDST3
.word 0 ;DMCTR3
.word 0 ;DMSFC3
.word 0 ;DMMCR3
.word 0 ;DMSRC4
.word 0 ;DMDST4
.word 0 ;DMCTR4
.word 0 ;DMSFC4
.word 0 ;DMMCR4
.word 0 ;DMSRC5
.word 0 ;DMDST5
.word 0 ;DMCTR5
.word 0 ;DMSFC5
.word 0 ;DMMCR5
.word 0 ;DMSRCP, no extended addressing
.word 0 ;DMDSTP, no extended addressing
.word 4 ;DMIDX0
.word 0 ;DMIDX1
.word -(3*4-1) ;DMFRI0
.word 0 ;DMFRI1
.word 0 ;DMGSA
.word 0 ;DMGDA
.word 0 ;DMGCR
.word 0 ;DMGFR
.word 0 ;XSRCDP
.word 0 ;XDSTDP
.word 0 ;DMGSA1
.word 0 ;DMGDA1
.word 0 ;DMGCR1
.word 0 ;DMGFR1
.word 0 ;DMGSA2
.word 0 ;DMGDA2
.word 0 ;DMGCR2
.word 0 ;DMGFR2
.word 0 ;DMGSA3
.word 0 ;DMGDA3
.word 0 ;DMGCR3
.word 0 ;DMGFR3
.word 0 ;DMGSA4
.word 0 ;DMGDA4
.word 0 ;DMGCR4
.word 0 ;DMGFR4
.word 0 ;DMGSA5
.word 0 ;DMGDA5
.word 0 ;DMGCR5
.word 0 ;DMGFR5
.end
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