codec_cnst.h54

c5x中关于codec的实验

;*************************************************************************
;               		SJTU DSP Tech. Center
;        Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
;  History:
;		Date		Authors			Changes
;		2003/08/30	Fu Xuan			Created.
;*************************************************************************

;*************************************************************************
;	Const For TLC320AD50C
;*************************************************************************


;*************************************************************************
;				Data Format in Secondary Communication
;   D15 D14 D13 |D12 D11 D10 D9 D8| D7 D6 D5 D4 D3 D2 D1 D0
;            |  |     register    |   register
;           R/W |     address     |     data
;*************************************************************************
;the following 5 addresses below have been shifted accorrding to the
;					              request of Secondary Communication
REG0_ADDR	.set	0x0000
REG1_ADDR	.set	0x0100
REG2_ADDR	.set	0x0200
REG3_ADDR	.set	0x0300
REG4_ADDR	.set	0x0400


;*************************************************************************
;   nop register
;	D7		D6		D5		D4		D3		D2		D1		D0
;														  2nd Comm. Req
;*************************************************************************
REG0_SECONDARY_COMM		.set	0b


;*************************************************************************
;   control register 1
;	D7		D6		D5		D4		D3		D2		D1		D0
; Software	SW    Select  Select      Monitor    Digital   16bit
;  Reset   Power   AUX		AUX      Amplifier   Loopback   DAC
;			down   ADC	  Monitor      Gain
;*************************************************************************
REG1_SW_RESET		.set	10000000b
REG1_SW_PWDN		.set	01000000b

REG1_AUX_ADC		.set	00100000b

REG1_AUX_MONITOR	.set	00010000b

REG1_MAG_N18DB		.set	00001100b
REG1_MAG_N8DB		.set	00001000b
REG1_MAG_0DB		.set	00000100b
REG1_MAG_MUTE		.set	00000000b

REG1_D_LOOPBACK		.set	00000010b

REG1_DAC_16MODE		.set	00000001b
REG1_DAC_15P1MODE	.set	00000000b


;*************************************************************************
;   control register 2
;	D7		D6		D5		D4		D3		D2		D1		D0
;  Flag	  Phone   Dec FIR  16bit  Analog	 /FSD
;  Value   Mode   Overflow  mode  Loopback
;*************************************************************************
REG2_PHONE_ENABLE	.set 	01000000b
REG2_PHONE_DISABLE	.set	00000000b

REG2_ADC_16MODE		.set	00010000b
REG2_ADC_15P1MODE	.set	00000000b

REG2_AL_ENABLE		.set	00001000b
REG2_AL_DISABLE		.set	00000000b


;*************************************************************************
;   control register 3
;	D7		D6		D5		D4		D3		D2		D1		D0
;	slave number	   number of SCLKs between /FS and /FSD
;*************************************************************************


;*************************************************************************
;   control register 4
;	D7		D6		D5		D4		D3		D2		D1		D0
; internal	 sampling frequency		Analog Input	Analog Output
;	DPLL		select (N)				Gain			Gain
;
;   Fs = MCLK/(128*N), D7=0
;		 MCLK/(512*N), D7=1
;	SLCK = 256 * Fs
;*************************************************************************
REG4_AIG_MUTE		.set	00001100b
REG4_AIG_12DB		.set	00001000b
REG4_AIG_6DB		.set	00000100b
REG4_AIG_0DB		.set	00000000b

REG4_AOG_MUTE		.set	00000011b
REG4_AOG_N12DB		.set	00000010b
REG4_AOG_N6DB		.set	00000001b
REG4_AOG_0DB		.set	00000000b

REG4_N_1			.set	00010000b
REG4_N_2			.set	00100000b
REG4_N_3			.set	00110000b
REG4_N_4			.set	01000000b
REG4_N_5			.set	01010000b
REG4_N_6			.set	01100000b
REG4_N_7			.set	01110000b
REG4_N_8			.set	00000000b

REG4_DPLL_ENABLE	.set	10000000b
REG4_DPLL_BYPASS	.set	00000000b

;end of codec_cnst.h54