📄 codec.s54
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;******************************************************************************
; SJTU DSP Tech. Center
; Copyright (c) 2002 SJTU DSP Tech. Center. All Rights Reserved.
; History:
; Date Authors Changes
; 2003/08/30 Fu Xuan Created.
; 2007/09/20 Chen Yu Changed.
;******************************************************************************
.mmregs
;functions
.global _c_int00
.global _leds_on
.global _led1_on
.global _led2_on
.global _led3_on
.global _led4_on
.global _leds_off
.global _led1_off
.global _led2_off
.global _led3_off
.global _led4_off
.global _init_mcbsp
.global _init_codec
.global _init_dma
.global _enable_codec
.global _processing
;variables
.global _input_pingpong_flag
.global _output_pingpong_flag
.global _dmac0_int_flag
.global _dmac4_int_flag
.global _in_data_ping
.global _in_data_pong
.global _out_data_ping
.global _out_data_pong
data_size .set 1024
frame_size_1 .set 2
arg_2 .set frame_size_1+1
arg_3 .set arg_2+1
arg_4 .set arg_3+1
frame_size_2 .set 0
arg_out_buf .set frame_size_2+1
arg_N .set arg_out_buf+1
.include "dsp_cnst.h54"
.text
;=================================================================
_leds_on:
portr USER_REG, *(AL)
or #0x000F, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=1
portw *(AL), USER_REG ;LED0、LED1、LED2、LED3 shine
ret
_led1_on;
portr USER_REG, *(AL)
or #0x0001, A
portw *(AL), USER_REG
ret
_led2_on:
portr USER_REG, *(AL)
or #0x0002, A
portw *(AL), USER_REG
ret
_led3_on:
portr USER_REG, *(AL)
or #0x0004, A
portw *(AL), USER_REG
ret
_led4_on:
portr USER_REG, *(AL)
or #0x0008, A
portw *(AL), USER_REG
ret
;=================================================================
_leds_off:
portr USER_REG, *(AL)
and #0xFFF0, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=0
portw *(AL), USER_REG ;LED0, LED1, LED2, LED3 shut
ret
_led1_off:
portr USER_REG, *(AL)
and #0xFFFE, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=0
portw *(AL), USER_REG ;LED0, LED1, LED2, LED3 shut
ret
_led2_off:
portr USER_REG, *(AL)
and #0xFFFD, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=0
portw *(AL), USER_REG ;LED0, LED1, LED2, LED3 shut
ret
_led3_off:
portr USER_REG, *(AL)
and #0xFFFB, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=0
portw *(AL), USER_REG ;LED0, LED1, LED2, LED3 shut
ret
_led4_off:
portr USER_REG, *(AL)
and #0xFFF7, A ;USR_LED3=USR_LED2=USR_LED1=USR_LED0=0
portw *(AL), USER_REG ;LED0, LED1, LED2, LED3 shut
ret
;=================================================================
_init_mcbsp: ;all ARs can be free used
stm #MCBSP2_CNST, AR2
stm #SPSA2, AR3
stm #(15-1), BRC
rptb MCBSP2_loop-1
ld *AR2+, A ;load sub-address into acc
stl A, *AR3+ ;load sub-address into SPSA2, AR3->SPSD2
ld *AR2+, A ;store data into acc
stl A, *AR3- ;store data into SPSD2, AR3->SPSA2
MCBSP2_loop:
ret
;=================================================================
_init_codec:
pshm ST0
pshm ST1
ssbx INTM ;disable all interrupts
;select codec as McBSP2 signal resource
stm #0x0, AR2
portw *(AR2), MISC ;MISC=0x0000
portw *(AR2), CODEC_CLK ;CODEC_CLK=0x0000
;set CODEC control register 0
stm #0x80, AR2
portw *(AR2), CODEC_L
stm #0x01, AR2 ;Left Channel DAC attenuation =
portw *(AR2), CODEC_H
call wait_codec_cmd_ready
;set CODEC control register 1
stm #0x80, AR2
portw *(AR2), CODEC_L
stm #0x01, AR2
portw *(AR2), CODEC_H
call wait_codec_cmd_ready
;set CODEC control register 2
;CODEC_CTL2
;PDAD=0, disable ADC power down
;BYPS=0, enable high pass filter
;PDDA=0, disable DAC power down
;ATC=0, attenuation of the two channels set indepandently
;IZD=0, disable infinitely zero detection
;OUT=1, enable DAC output
;DEM[1,0]=01, disable de-emphasis
;MUT=0, disable soft mute
stm #0x00, AR2
portw *(AR2), CODEC_L
stm #0x00, AR2
portw *(AR2), CODEC_H
call wait_codec_cmd_ready
;set CODEC control register 3
;LOP=0, disable ADC to DAC loop-back
;FMT[1,0]=00, Format 0
;LRP=0, left channel is 'H', right channel is 'L'
stm #0x00, AR2
portw *(AR2), CODEC_L
stm #0x00, AR2
portw *(AR2), CODEC_H
call wait_codec_cmd_ready
popm ST1
popm ST0
ret
wait_codec_cmd_ready:
portr MISC, *(AL) ;AL<-MISC
bitf *(AL), #0x0080 ;test CODEC_RDY bit in MISC
bc wait_codec_cmd_ready, TC
ret
;=================================================================
_init_dma:
stm #0x5180, DMPREC ;AUTOIX=1, all DMA channels use its own global registers
;DPRC[4,0]=11, set DMA0, DMA4 to high priority
;INTOSEL=10, use DMA1,2,3 interrupt
stm #DMA_CNST, AR3
stm #0, DMSA
stm #DMSDI, AR2
stm #31-1, BRC
rptb END_INIT_DMA-1
mvdd *AR3+, *AR2
mvdd *AR3+, *AR2
END_INIT_DMA:
ret
;=================================================================
_enable_codec:
;LED0 shines to show that all initializations have finished
portr USER_REG, *(AL)
or #0x0001, A ;USR_LED0=1
portw *(AL), USER_REG
;ready for data receive
stm #0x1040, IMR ;set IMR to enable DMA0, DMA4 Interrupt
stm #0xFFFF, IFR ;set IFR to clear pending interrupt
;enable interrupts
stm #0x00E0, PMST ;PMST: IPTR=1, MP/MC#=1, OVLY=1
rsbx INTM ;enable all interrupts
;enable channel 0 and 4 of DMA
ldm DMPREC, A ;set DE[0]=1, DE[4]=1 to enable channel 0, 4
or #0x0011, A
stlm A, DMPREC
;enable McBSP2 (set RRST=XRST=1)
stm #SPSA2, AR2
st #0, *AR2+ ;SPSA2<-SPCR12, AR2<-SPSD2
orm #0x0001, *AR2- ;/RRST=1, AR2<-SPSA2
st #1, *AR2+ ;SPSA2<-SPCR22, AR2<-SPSD2
orm #0x0001, *AR2- ;/XRST=1, AR2<-SPSA2
ret
;******************************************************************************
;** Function: _processing
;** Description:
;** Processing the data received from AD and send the result to DA
;******************************************************************************
_processing:
;put your information processing program here
;at this time, we just send the raw data back to DA without any processing
stlm A, AR2 ;AR2<-arg_in
mvdk *SP(arg_out_buf), AR3
ld *SP(arg_N), A
SUB #1, A
stlm A, BRC
rptb END_PROCESSING-1
mvdd *AR2+, *AR3+
mvdd *AR2+, *AR3+
END_PROCESSING:
ret
.sect "Init_table"
;******************************************************************************
; McBSP2 Init Constants
;******************************************************************************
MCBSP2_CNST:
.word 0 ;sub address==SPCR12
.word 0x0000 ;SPCR12
;DLB=0, disable digital loop
;RJUST=00, right justified, zero extended in DRR[1,2]
;CLKSTP=00, disable clock stop mode
;DXENA=0, close DX enable
;ABIS=0, disable A-bis mode
;RINTM=00, RINT driven by RRDY
;RSYNCERR=0, no error in received frame sync signal
;RFULL=0, RBR[1,2] are not full
;RRDY, receiving is not ready
;/RRST=0, reset the receiving
.word 1 ;sub address==SPCR22
.word 0x0100 ;SPCR22
;FREE=0, disable free run mode
;SOFT=1, enable SOFT mode
;/FRST=0, reset the frame sync signal generator
;/GRST=0, reset the sample rate generator
;XINTM=00, XINT driven by XRDY
;XSYNCERR=0, no error in transmitted frame sync signal
;/XEMPTY=0, XSR[1,2] are not empty
;XRDY=0, transmition is not ready
;/XRST=0, reset the transmition
.word 2 ;sub address==RCR12
.word 0x0140 ;RCR12
;RFRLEN1=0000001, 2 words per frame
;RWDLEN1=010, 16 bits per word
.word 3 ;sub address==RCR22
.word 0x0000 ;RCR22
;RPHASE=0, single-phase frame
;RFRLEN2=0000000, ignored
;RWDLEN2=000, ignored
;RCOMPAND=00, no expandition, MSB first
;RFIG=0, frame synchronized in each receiving
;RDATDLY=00, 0 bit delay
.word 4 ;sub address==XCR12
.word 0x0140 ;XCR12
;XFRLEN1=0000001, 2 words per frame
;XWDLEN1=010, 16 bits per word
.word 5 ;sub address==XCR22
.word 0x0000 ;XCR22
;XPHASE=0, single-phase frame
;XFRLEN2, XWDLEN2 are ignored
;XCOMPAND=00, no expandition, MSB first
;XFIG=0, frame synchronized in each transmition
;XDATDLY=00, 0 bit delay
.word 6 ;sub address==SRGR12
.word 0 ;SRGR12
.word 7 ;sub address==SRGR22
.word 0 ;SRGR22
.word 8 ;sub address==MCR12
.word 0 ;MCR12
;RMCM=0, enable all 128 channels
.word 9 ;sub address==MCR22
.word 0 ;MCR22
;XMCM=00, enable all 128 channels
.word 10 ;sub address==RCERA2
.word 0 ;RCERA2
.word 11 ;sub address==RCERB2
.word 0 ;RCERB2
.word 12 ;sub address==XCERA2
.word 0 ;XCERA2
.word 13 ;sub address==XCERB2
.word 0 ;XCERB2
.word 14 ;sub address==PCR1
.word 0x0003 ;XIOEN=RIOEN=0, DX, FSX, CLKX, DR, FSR, CLKR, CLKS are used for McBSP
;FSXM=FSRM=0, external driven
;CLKXM=CLKRM=0, external driven
;FSXP=FSRP=0, high-valid frame sync impulse
;CLKXP=1, transmit data sampled on the falling edge of CLKX
;CLKRP=1, receive data sampled on the rising edge of CLKR
;******************************************************************************
; DMA Init Constants
;******************************************************************************
DMA_CNST:
.word DRR12 ;DMSRC0, McBSP2 receive register
.word _in_data_ping ;DMDST0
.word data_size-1 ;DMCTR0, (number of elements)-1
.word 0x3000 ;DMSFC0
;DSYN=0011b, McBSP2 receive event
;DBLW=0, single word mode
;FRMCNT=0, one frame transferred each time
.word 0xE045 ;DMMCR0
;AUTOINIT=1, enable auto-initializtion
;DINM=1, generate interrupt according to IMOD
;IMOD=1, generate interrupt at the end of one frame or one block
;CTMOD=0, multi-frame mode
;SIND=000, source address is not modified
;DMS=01, source address is in data space
;DIND=001, destination address is modifed by post-add 1
;DMD=01, destination address is in data space
.word 0 ;DMSRC1
.word 0 ;DMDST1
.word 0 ;DMCTR1
.word 0 ;DMSFC1
.word 0 ;DMMCR1
.word 0 ;DMSRC2
.word 0 ;DMDST2
.word 0 ;DMCTR2
.word 0 ;DMSFC2
.word 0 ;DMMCR2
.word 0 ;DMSRC3
.word 0 ;DMDST3
.word 0 ;DMCTR3
.word 0 ;DMSFC3
.word 0 ;DMMCR3
.word _out_data_ping ;DMSRC4
.word DXR12 ;DMDST4, McBSP2 transmit register
.word data_size-1 ;DMCTR4, (number of elements)-1
.word 0x4000 ;DMSFC4
;DSYN=0100b, McBSP2 transmit event
;DBLW=0, single word mode
;FRMCNT=0, one frame transferred each time
.word 0xE141 ;DMMCR4
;AUTOINIT=1, enable auto-initialization
;DINM=1, generate interrupt according to IMOD
;IMOD=1, generate interrupt at the end of one frame or one block
;CTMOD=0, multi-frame mode
;SIND=001, source address is modified by post-add 1
;DMS=01, source address is in data space
;DIND=000, destination address is not modified
;DMD=01, destination address is in data space
.word 0 ;DMSRC5
.word 0 ;DMDST5
.word 0 ;DMCTR5
.word 0 ;DMSFC5
.word 0 ;DMMCR5
.word 0 ;DMSRCP, no extended addressing
.word 0 ;DMDSTP, no extended addressing
.word 0 ;DMIDX0
.word 0 ;DMIDX1
.word 0 ;DMFRI0
.word 0 ;DMFRI1
.word DRR12 ;DMGSA0, global source address reload register
.word _in_data_pong ;DMGDA0, global destination address reload register
.word data_size-1 ;DMGCR0, global element count reload register
.word 0 ;DMGFR0, global frame count reload register
.word 0 ;XSRCDP
.word 0 ;XDSTDP
.word 0 ;DMGSA1
.word 0 ;DMGDA1
.word 0 ;DMGCR1
.word 0 ;DMGFR1
.word 0 ;DMGSA2
.word 0 ;DMGDA2
.word 0 ;DMGCR2
.word 0 ;DMGFR2
.word 0 ;DMGSA3
.word 0 ;DMGDA3
.word 0 ;DMGCR3
.word 0 ;DMGFR3
.word _out_data_pong ;DMGSA4
.word DXR12 ;DMGDA4
.word data_size-1 ;DMGCR4
.word 0 ;DMGFR4
.word 0 ;DMGSA5
.word 0 ;DMGDA5
.word 0 ;DMGCR5
.word 0 ;DMGFR5
;******************************************************************************
; Interrupt vector table
;******************************************************************************
.sect "vectors"
int_reset:
b _c_int00
nop
nop
.space 84*16
int_damc0:
bd DMAC0_ISR ;read data from DRR11 to INPUT_PINGPONG0/1
pshm ST0
pshm ST1
.space 20*16
int_dmac4:
bd DMAC4_ISR ;send data from OUTPUT_PINGPONG0/1 to DXR11
pshm ST0
pshm ST1
.space 12*16
;*********************** Interrupt Service Routine ****************************
.text
;******************************************************************************
;** Function: DMAC0_ISR
;** Description:
;** DMAC0 ISR for McBSP1 receive
;******************************************************************************
DMAC0_ISR:
pshm AL
pshm AH
pshm AG
bitf *(_input_pingpong_flag), #1 ;TC <- ( _input_pingpong_flag & 1 )
stm #DMGDA0, DMSA ;DMSA <- #DMGDA
bc IN_PINGPONG1_SET, TC
;if input_pingpong_flag is 0, stroe #INPUT_PINGPONG_0 in DMSDN
bd IN_PROCESS_EXIT
stm #_in_data_pong, DMSDN ;(DMGDA) <- #_in_data_ping
;if input_pingpong_flag is 1, stroe #INPUT_PINGPONG_1 in DMSDN
IN_PINGPONG1_SET:
stm #_in_data_ping, DMSDN ;(DMGDA) <- #_in_data_pong
IN_PROCESS_EXIT:
xorm #1, *(_input_pingpong_flag) ;alter input_pingpong_flag when each interrupt come
st #1, *(_dmac0_int_flag) ;set dmac0_int_flag when each interrupt come
ldm DMPREC, A ;enable DMA0
or #0x0001, A
stlm A, DMPREC
popm AG
popm AH
popm AL
popm ST1
popm ST0
rete
;******************************************************************************
;** Function: DMAC4_ISR
;** Description:
;** DMAC4 ISR for McBSP2 send
;******************************************************************************
DMAC4_ISR:
pshm AL
pshm AH
pshm AG
bitf *(_output_pingpong_flag), #1
stm #DMGSA4, DMSA ;DMSA <- #DMSRC4
bc OUT_PINGPONG1_SET, TC
;if output_pingpong_flag is 0, store #OUTPUT_PINGPONG_0 in DMSDN
bd OUT_PROCESS_EXIT
stm #_out_data_pong, DMSDN ;DMSDN->DMSRC4
;if output_pingpong_flag is 1, store #OUTPUT_PINGPONG_1 in DMSDN
OUT_PINGPONG1_SET:
stm #_out_data_ping, DMSDN ;DMSDN->DMSRC4
OUT_PROCESS_EXIT:
xorm #1, *(_output_pingpong_flag);alter output_pingpong_flag when each interrupt come
st #1, *(_dmac4_int_flag) ;set dmac4_int_flag when each interrupt come
ldm DMPREC, A ;enable DMA4
or #0x0010, A
stlm A, DMPREC
popm AG
popm AH
popm AL
popm ST1
popm ST0
rete
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