ctc_tx_fsm.v

上传的是WIMAX系统中

///*********************************************************************
/// Copyright(c) 2006, ZTE.
/// All rights reserved.
///
/// Project name : ZXMBW-250(WIMAX)
/// File name    : ctc_tx_fsm.v
/// Author       : wangjinshan  yuanliuqing
/// Department   : 2nd IC department
/// Email        : [e-mail]
///
/// Module_name  : ctc_tx_fsm
/// Called by    : ctc_decoder  module
///---------------------------------------------------------------------
/// Module Hiberarchy:
/// ctc_tx_fsm-----|----ctc_tx_arb
///---------------------------------------------------------------------
///
/// Release History:
///---------------------------------------------------------------------
/// Version     |    Date     |       Author Description
///---------------------------------------------------------------------
/// 1.0-0       | 2006-06-10  | 建立文件
///---------------------------------------------------------------------
/// 1.1-0       | 2006-10-09  | 更改为3个译码核
///---------------------------------------------------------------------
// Main Function:
/// 1、CTC译码核输出状态机
///*********************************************************************

`timescale 1ns/100ps

module ctc_tx_fsm
  (
    ///interface with ctc_fifo1
    ///input
    input       [31:0] ctc_fifo1_rddat,             ///core1输出FIFO数据线
    input       [8:0]  ctc_fifo1_usedw,             ///core1输出FIFO空间使用
    input              ctc_fifo1_empty,             ///core1输出FIFO空信号
    ///output
    output reg         ctc_fifo1_rdreq,             ///core1输出FIFO读信号

    ///interface with ctc_fifo2
    ///input
    input       [31:0] ctc_fifo2_rddat,
    input       [8:0]  ctc_fifo2_usedw,
    input              ctc_fifo2_empty,
    ///output
    output reg         ctc_fifo2_rdreq,

    ///interface with ctc_fifo3
    ///input
    input       [31:0] ctc_fifo3_rddat,
    input       [8:0]  ctc_fifo3_usedw,
    input              ctc_fifo3_empty,
    ///output
    output reg         ctc_fifo3_rdreq,

    ///interface with post_ctc_fifo
    ///input
    input              full_post_ctc_fifo,          ///数据输出FIFO满信号
    input              empty_post_ctc_fifo,         ///数据输出FIFO空信号
    input       [8:0]  wrusedword_post_ctc_fifo,    ///数据输出FIFO空间使用
    ///output
    output reg         wr_post_ctc_fifo,            ///数据输出FIFO写信号
    output reg         eop_wr_post_ctc_fifo,        ///数据输出FIFO写结束信号
    output reg  [31:0] dat_wr_post_ctc_fifo,        ///数据输出FIFO写数据线

    ///system signals
    input              sys_clk,                     ///系统时钟信号
    input              reset_b,                     ///输入复位信号

    output reg  [15:0] tx_counter1_nc,
    output reg  [15:0] tx_counter2_nc,
    output reg  [15:0] tx_counter3_nc               
 );
///*********************************************************************
///local parameter define：(本地参数：)
///*********************************************************************
/// State codes definitions:
parameter       IDLE        = 10'b00_0000_0001;     ///空闲
parameter       RD_FIFO1    = 10'b00_0000_0010;     ///读core1的输出FIFO
parameter       WT1         = 10'b00_0000_0100;     ///等待一个cycle
parameter       WR_FIFO1    = 10'b00_0000_1000;     ///写FIFO
parameter       RD_FIFO2    = 10'b00_0001_0000;     ///读core2的输出FIFO
parameter       WT2         = 10'b00_0010_0000;     ///等待一个cycle
parameter       WR_FIFO2    = 10'b00_0100_0000;     ///写FIFO
parameter       RD_FIFO3    = 10'b00_1000_0000;     ///读core3的输出FIFO
parameter       WT3         = 10'b01_0000_0000;     ///等待一个cycle
parameter       WR_FIFO3    = 10'b10_0000_0000;     ///写FIFO

///*********************************************************************
///内部信号定义
///*********************************************************************
reg     [9:0]   st_current;
reg     [9:0]   st_next;

reg     [15:0]  r0_cnt;
reg     [15:0]  r1_cnt;
reg     [15:0]  r2_cnt;
reg     [15:0]  p_len;
///reg     [15:0]  r0_cnt_next;
///reg     [15:0]  r1_cnt_next;
///reg     [15:0]  r2_cnt_next;
///reg     [15:0]  p_len_next;
wire            core1_gnt;
wire            core2_gnt;
wire            core3_gnt;
    
///*********************************************************************
///主程序代码：
///*********************************************************************
always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        tx_counter1_nc <= 1'b0;
    else
    begin
        if(st_current==RD_FIFO1)
            tx_counter1_nc <= tx_counter1_nc + 1'b1;
        else
            tx_counter1_nc <= tx_counter1_nc;
    end
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        tx_counter2_nc <= 1'b0;
    else
    begin
        if(st_current==RD_FIFO2)
            tx_counter2_nc <= tx_counter2_nc + 1'b1;
        else
            tx_counter2_nc <= tx_counter2_nc;
    end
end

always @(posedge sys_clk or negedge reset_b) begin
    if(!reset_b)
        tx_counter3_nc <= 1'b0;
    else
    begin
        if(st_current==RD_FIFO3)
            tx_counter3_nc <= tx_counter3_nc + 1'b1;
        else
            tx_counter3_nc <= tx_counter3_nc;
    end
end
///*********************************************************************
	    
/// Current State Logic (sequential)
/// state_intialization
always @(posedge sys_clk or negedge reset_b)
    if (~reset_b)
        st_current <= IDLE;
    else
        st_current <= st_next;
       // state machine

always @(*) begin
    st_next = st_current;
    case(st_current)
        IDLE:
            if(core1_gnt)
                st_next = RD_FIFO1;
            else if(core2_gnt)
                st_next = RD_FIFO2;
            else if(core3_gnt)
                st_next = RD_FIFO3;
            else
                st_next = IDLE;

        RD_FIFO1: st_next = WT1;
        WT1:
            if(ctc_fifo1_usedw >= (p_len[8:0]-1'b1))
                st_next = WR_FIFO1;
            else
                st_next = WT1;
        WR_FIFO1:
            if(r0_cnt<p_len)
                st_next = WR_FIFO1;
            else
                st_next = IDLE;

        RD_FIFO2:
               st_next = WT2;
        WT2:
            if(ctc_fifo2_usedw >= (p_len[8:0]-1'b1))
                st_next = WR_FIFO2;
            else
                st_next = WT2;
        WR_FIFO2:
            if(r1_cnt<p_len)
                st_next = WR_FIFO2;
            else
                st_next = IDLE;

        RD_FIFO3:
            st_next = WT3;
        WT3:
            if(ctc_fifo3_usedw >= (p_len[8:0]-1'b1))
                st_next = WR_FIFO3;
            else
                st_next = WT3;
        WR_FIFO3:
            if(r2_cnt<p_len)
                st_next = WR_FIFO3;
            else
                st_next = IDLE;
        default: st_next = IDLE;
   endcase
end //state machine

///**************************************************************************
///生成计数器r0_cnt,r1_cnt,r2_cnt及包长plen
///将if_else结构改成case结构
///Fang.yongzhong
///**************************************************************************
/*
always @(posedge sys_clk or negedge reset_b) begin
    if (~reset_b) begin
        r0_cnt <= 16'b0;
        r1_cnt <= 16'b0;
        r2_cnt <= 16'b0;
        p_len  <= 16'b0;
    end
    else begin
        r0_cnt <= r0_cnt_next;
        r1_cnt <= r1_cnt_next;
        r2_cnt <= r2_cnt_next;
        p_len  <= p_len_next;
    end
end  

always @(*) begin
    case(st_current)
        RD_FIFO1:
            r0_cnt_next = 16'b0;
        WR_FIFO1:
            r0_cnt_next = r0_cnt + 1'b1;
        RD_FIFO2:
            r1_cnt_next = 16'b0;
        WR_FIFO2:
            r1_cnt_next = r1_cnt + 1'b1;
        RD_FIFO3:
            r2_cnt_next = 16'b0;
        WR_FIFO3:
            r2_cnt_next = r2_cnt + 1'b1;
        WT1:
            if(~|ctc_fifo1_rddat[1:0])                          
                p_len_next = (ctc_fifo1_rddat[15:0]>>2) + 16'h2;
            else                                                
                p_len_next = (ctc_fifo1_rddat[15:0]>>2) + 16'h3;