sliding_win_fsm.v

上传的是WIMAX系统中

                begin
                    if( clr_cal_buf )
                        wr_alpha_buf_delay_line <= 1'b0;
                    else
                        wr_alpha_buf_delay_line[WIN_SIZE-1'b1:0] 
                            <=  {wr_alpha_buf_delay_line[WIN_SIZE-2'd2:0],wr_alpha_buf};
                end
        end

    

    //*************************************************************************
    //generate beta_sel
    //*************************************************************************
    
    reg [7:0] beta_sel_counter;
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    beta_sel <= 1'b0;               
                end
            else 
                begin
                    if( clr_cal_buf )
                        beta_sel <= 1'b0;   
                    else if( beta_sel_counter==(WIN_SIZE-2'd2) )// <= (WIN_SIZE-1'd1)
                        begin
                            case( beta_sel )
                                2'b00:
                                    beta_sel <= 2'b01;                                
                                2'b01:
                                    beta_sel <= 2'b10;
                                2'b10:
                                    beta_sel <= 2'b01;
                                default:
                                    beta_sel <= 2'b00;
                            endcase
                        end
                    else
                        beta_sel <= beta_sel;
                end
        end

    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    new_beta_cal0 <= 1'b0;
                    new_beta_cal1 <= 1'b0;               
                end
            else
                begin
                    if( beta_sel==2'b01 && beta_sel_counter==(WIN_SIZE-2'd2) )
                        begin
                            new_beta_cal0 <= 1'b1;
                            new_beta_cal1 <= 1'b0;
                        end
                    else if( beta_sel==2'b10 && beta_sel_counter==(WIN_SIZE-2'd2) )
                        begin
                            new_beta_cal0 <= 1'b0;
                            new_beta_cal1 <= 1'b1;
                        end
                    else
                        begin
                            new_beta_cal0 <= 1'b0;
                            new_beta_cal1 <= 1'b0;
                        end
                end
        end
            
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                begin
                    beta_sel_counter <= 1'b0;                
                end
            else 
                begin
                    if( clr_cal_buf )
                        beta_sel_counter <= 1'b0;
                    else if( beta_sink_val0 || beta_sink_val1 )
                        begin
                            if( beta_sel_counter==(WIN_SIZE-1'b1) )
                                beta_sel_counter <= 1'b0;
                            else
                                beta_sel_counter <= beta_sel_counter + 1'b1;                        
                        end
                    else
                        beta_sel_counter <= beta_sel_counter;
                end
        end


    //*************************************************************************
    //sliding_win_state
    //*************************************************************************
    
    reg [7:0]   slide_win_state_current;
    reg [7:0]   slide_win_state_next;
    //fsm state definitions
    parameter   READY           =  8'b0000_0001,
                FILL_IN0        =  8'b0000_0010,
                FILL_IN1        =  8'b0000_0100,
                PROCESS_HEAD0   =  8'b0000_1000,
                PROCESS_HEAD1   =  8'b0001_0000, 
                PROCESS_MID     =  8'b0010_0000,
                PROCESS_TAIL    =  8'b0100_0000,
                IDLE            =  8'b1000_0000;
    
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                slide_win_state_current <= READY;
            else
                slide_win_state_current <= slide_win_state_next;
        end
    
    always @ ( * )
        begin
            case( slide_win_state_current )
                READY:
                    begin
                        if( sop_source )
                            slide_win_state_next = FILL_IN0;
                        else
                            slide_win_state_next = READY;
                    end
                FILL_IN0:
                    begin
                        if( block_cir_buf_wr_counter == WIN_SIZE-2'd2 )
                            slide_win_state_next = FILL_IN1;
                        else
                            slide_win_state_next = FILL_IN0;
                    end
                FILL_IN1:
                    begin
                        if( block_cir_buf_wr_counter == WIN_SIZE*2-2'd2 )
                            slide_win_state_next = PROCESS_HEAD0;
                        else
                            slide_win_state_next = FILL_IN1;                    
                    end
                PROCESS_HEAD0:
                    begin
                        if( block_cir_buf_wr_counter == WIN_SIZE*3-2'd2 )
                            slide_win_state_next = PROCESS_HEAD1;
                        else
                            slide_win_state_next = PROCESS_HEAD0;                     
                    end
                PROCESS_HEAD1:
                    begin
                        if( block_cir_buf_wr_counter == WIN_SIZE*4-2'd1 )//!!!
                            if(  packet_length==16'd24 )//eop_source ||
                                slide_win_state_next = PROCESS_TAIL;
                            else
                                slide_win_state_next = PROCESS_MID;
                        else
                            slide_win_state_next = PROCESS_HEAD1;                     
                    end
                PROCESS_MID:
                    begin
                        if( eop_source_pass_counter == WIN_SIZE-2'd1 )
                            slide_win_state_next = PROCESS_TAIL;
                        else
                            slide_win_state_next = PROCESS_MID;
                    end
                PROCESS_TAIL:
                    begin
                        if( eop_source_pass_counter == WIN_SIZE*2-2'd1 )
                            slide_win_state_next = IDLE;
                        else
                            slide_win_state_next = PROCESS_TAIL;                    
                    end
                IDLE:
                    begin
                        if( eop_sink )
                            slide_win_state_next = READY;
                        else
                            slide_win_state_next = IDLE; 
                    end
                default:
                    begin
                        slide_win_state_next = READY;
                    end
            endcase
        end
          
    //generate rd_cir_buf_cell0    
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                rd_cir_buf_cell0 <= 1'b0;                
            else 
                begin
                    case( slide_win_state_current )
                        PROCESS_HEAD0:
                            rd_cir_buf_cell0 <= 1'b1;
                        PROCESS_HEAD1://!((eop_source&&(packet_length!==16'd24)) ||
                            if( (block_cir_buf_wr_counter==(WIN_SIZE*4-2'd1))&&(packet_length==16'd24) ) 
                                rd_cir_buf_cell0 <= 1'b0;
                            else//PROCESS_TAIL output
                                rd_cir_buf_cell0 <= 1'b1;
                        PROCESS_MID:
                            rd_cir_buf_cell0 <= 1'b1;
                        default:
                            rd_cir_buf_cell0 <= 1'b0;
                    endcase
                end
        end
        
    //generate rd_cir_buf_cell1
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                rd_cir_buf_cell1 <= 1'b0;                
            else 
                begin
                    case( slide_win_state_current )
                        PROCESS_HEAD1:
                            begin
                                rd_cir_buf_cell1 <= 1'b1;
                            end
                        PROCESS_MID:
                            rd_cir_buf_cell1 <= 1'b1;
                        PROCESS_TAIL:
                            begin
                                if( win_parity_flag )// || (packet_length==16'd24) 
                                    rd_cir_buf_cell1 <= 1'b1;
                                else
                                    rd_cir_buf_cell1 <= 1'b0;
                            end
                        default:
                            rd_cir_buf_cell1 <= 1'b0;
                    endcase
                end
        end

    //generate rd_cir_buf_cell2
    always @ ( posedge clk_sys or negedge rst_b )
        begin
            if( !rst_b )
                rd_cir_buf_cell2 <= 1'b0;                
            else 
                begin
                    case( slide_win_state_current )
                        PROCESS_HEAD1:
                            if( (block_cir_buf_wr_counter==WIN_SIZE*4-2'd1)&&(packet_length!==16'd24) )//PROCESS_MID output
                                rd_cir_buf_cell2 <= 1'b1;
                            else
                                rd_cir_buf_cell2 <= 1'b0;
                        PROCESS_MID:
                            rd_cir_buf_cell2 <= 1'b1;
                        PROCESS_TAIL:
                            if( !win_parity_flag )
                                rd_cir_buf_cell2 <= 1'b1;
                            else
                                rd_cir_buf_cell2 <= 1'b0;
                        default:
                            rd_cir_buf_cell2 <= 1'b0;
                    endcase
                end
        end
endmodule  ///sliding_win_fsm