📄 boot.s
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#
# ***** BEGIN board Memory Space Set
# CS0 defined as Flash or SRAM at 0x00000000
lis r3,0x0000 # Flash at 0xffe00000
ori r3,r3,0x0001
stw r3,BR0(r4) # BR0=0x00000001
lis r3,0xffe0
ori r3,r3,0x0934
stw r3,OR0(r4) # OR0=0xffe00934
# CS3 not used
lis r3,0xff00
ori r3,r3,0x0934
stw r3,OR3(r4) # OR3=0xff000934
lis r3,0x1000
ori r3,r3,0x0000
stw r3,BR3(r4) # BR3=0x10000000
# CS4 defined as Flash or SRAM at 0x30000000
lis r3,0xff00
ori r3,r3,0x0934
stw r3,OR4(r4) # OR4=0xff000934
lis r3,0x2000
ori r3,r3,0x0001
stw r3,BR4(r4) # BR4=0x20000001
# CS1 defined as IO_SPACE AND TIMER at 0x40000000
lis r3,0xffe0
ori r3,r3,0x0970
stw r3,OR1(r4)
lis r3,0x4000
ori r3,r3,0x0401
stw r3,BR1(r4)
# CS5 defined as DSP Hpi Space at 0x50000000
lis r3,0xffe0
ori r3,r3,0x0924
stw r3,OR5(r4) # OR5=0xffe00924
lis r3,0x5000 #
ori r3,r3,0x0801
stw r3,BR5(r4) # BR5=0x50000801
# CS6 RESERVED
lis r3,0xffe0
ori r3,r3,0x0934
stw r3,OR6(r4)
lis r3,0x8000
ori r3,r3,0x0000
stw r3,BR6(r4)
# CS7 defined as FPGA switch Internal Register Space at 0x60000000
lis r3,0xff00
ori r3,r3,0x0940
stw r3,OR7(r4)
lis r3,0x6000
ori r3,r3,0x0801 #PORT SIZE = 16BIT
stw r3,BR7(r4)
# /* program the MPTPR */
li r3,0x0400 # MPTPR
sth r3,MPTPR(r4)
lis r3,0xFF20 # MAMR, disable refresh memory
ori r3,r3,0x6114
stw r3,MAMR(r4)
# CS2 defined as SDRAM at 0x00000000
#**************************************************************************#
# #
# Start Initiate SDRAM #
# #
#**************************************************************************#
addis r5,r0,INT_UPM_Table@ha # Get beginning address of UPM table
addi r5,r5,INT_UPM_Table@l
addi r6,r5,256 # Get end address of UPM table
lis r7,0x0000 # Load command: write,UPM,MAD=0
INT_UPM_Loop:
lwz r3,0(r5) # Get table entry
stw r3,MDR(r4) # Copy to MDR
stw r7,MCR(r4) # Issue command to MCR
addi r5,r5,4 # Point to next entry in table
addi r7,r7,1 # Increment MAD field of MCR command
cmp r5,r6 # Finished?
blt INT_UPM_Loop # If not, keep looping
li r3,0x0400 # MPTPR
sth r3,MPTPR(r4)
lis r5, 0x0000
ori r5, r5, 0x0088
stw r5, MAR(r4)
# Set CS2 related Config
lis r5, 0x8000
ori r5, r5, 0x4115
stw r5, MCR(r4)
lis r5, 0x8000
ori r5, r5, 0x4830
stw r5, MCR(r4)
lis r5, 0x8000
ori r5, r5, 0x4116
stw r5, MCR(r4)
# /* enable SDRAM refresh cycles */
lis r3,0xD0A0 # MAMR
ori r3,r3,0x6114
stw r3,MAMR(r4)
# Set OR2~~5 and BR2~~5 for SDRAM
lis r3,0xfc00 # SDRAM CS2 at 0x0 for 64M bytes
ori r3,r3,0x0A00
stw r3,OR2(r4)
lis r3,0x3000 #now SDRAM CS2 at 0x30000000 for 64M bytes
ori r3,r3,0x0081
stw r3,BR2(r4)
#**************************************************************************#
# #
# Initiate SDRAM complete #
# #
#**************************************************************************#
# /* Setup temperary initial stack pointer and small data base registers */
lis r11,__TEMP_SP_INIT@h
ori r1,r11,__TEMP_SP_INIT@l
#CopyProgFromFlashToSDRAM
bl CopyProgFromFlashToSDRAM
# Exchange CS2 and CS0 Address Space
# Change CS2 BaseAddress From 0x30000000 to 0x00000000
lis r3,0xfc00 # SDRAM CS2 at 0x0 for 64M bytes
ori r3,r3,0x0A00
stw r3,OR2(r4)
lis r3,0x0000
ori r3,r3,0x0081
stw r3,BR2(r4)
# Change CS0 BaseAddress From 0x00000000 to 0x30000000
lis r3,0x3000 # Flash at 0xffe00000
ori r3,r3,0x0001
stw r3,BR0(r4) # BR0=0x30000001
lis r3,0xffe0
ori r3,r3,0x0934
stw r3,OR0(r4) # OR0=0xffe00934
# /* Setup initial stack pointer and small data base registers */
lis r11,__SP_INIT@h
ori r1,r11,__SP_INIT@l
lis r13,_SDA_BASE_@h
ori r13,r13,_SDA_BASE_@l
lis r2,_SDA2_BASE_@h
ori r2,r2,_SDA2_BASE_@l
#
# ***** END board specific code for the board *****
#
# /* Call the Diab Data __init_main function. It will copy the .data
# section from ROM to RAM and will clear the .bss section. It will
# call the main() function, which is defined to be the next instruction
# after the call to __init_main. */
#
bl __init_main
#
#
main:
# /* Copy vector table to base address 0 */
# /*If copy flash to sdram the flowing copy is disable*/
lis r11,INT_Vectors@h # load current vector table base
ori r11,r11,INT_Vectors@l
cmpi 0,r11,0 # check if vector table is already at 0
beq INT_Vect_Base_Move # if so, skip vector copy
li r12,0x800 # load # of longwords in vector table
mtspr CTR,r12 # move to loop counter register
li r12,0 # load copy-to address
li r9,0 # load index
INT_Vect_Copy:
lwzx r10,r11,r9 # load word from source
stwx r10,r12,r9 # store word to destination
addi r9,r9,4 # move index to next longword
bdnz INT_Vect_Copy # if loop counter not 0, keep copying
#
# /* Move vector table base address to 0 */
#
INT_Vect_Base_Move:
mfmsr r12 # get current MSR
rlwinm r12,r12,0,26,24 # clear IP bit
mtmsr r12 # write out new MSR
#
# /* Setup the vectors loaded flag to indicate to other routines in the
# system whether or not all of the default vectors have been loaded.
# If INT_Loaded_Flag is 1, all of the default vectors have been loaded.
# Otherwise, if INT_Loaded_Flag is 0, registering an LISR causes the
# default vector to be loaded.*/
#
addis r12,r0,INT_Loaded_Flag@ha # get upper 16 bits of address
li r11,1 # clear the r11 register
stw r11,INT_Loaded_Flag@l(r12) # store 1 to INT_Loaded_Flag
#
# /* Initialize the system stack pointers. This is done after the BSS is
# clear because the TCD_System_Stack pointer is a BSS variable!. */
#
lis r4,__RTOS_MEMORY@h
ori r4,r4,__RTOS_MEMORY@l # load end of BSS section
addi r1,r4,4 # move to next available space
addis r1,r1,SYSTEM_SIZE@ha # add in our system stack size
addi r1,r1,SYSTEM_SIZE@l
addi r4,r1,-8 # allocate space for the EABI frame
#
# /* Save the current System stack to TCD_System_Stack. */
#
addis r10,r0,TCD_System_Stack@ha # get upper 16 bits and < 16 bits
stw r4,TCD_System_Stack@l(r10) # store the current stack
mr r14,r4 # save in preserved register
#
# TMD_HISR_Stack_Ptr = (VOID *) current stack address;
#
addi r4,r4,8 # move past system stack
addis r10,r0,TMD_HISR_Stack_Ptr@ha # get upper 16 bits and < 16 bits
stw r4,TMD_HISR_Stack_Ptr@l(r10) # store the current HISR stack
#
# /* Store the max size of the Timer HISR stack to TMD_HISR_Stack_Size. */
# TMD_HISR_Stack_Size = TIMER_SIZE;
#
li r9,TIMER_SIZE # load Timer HISR stack size
addis r10,r0,TMD_HISR_Stack_Size@ha # get upper 16 bits and < 16 bits
stw r9,TMD_HISR_Stack_Size@l(r10) # store the Timer HISR stack size
#
# /* Store the current Timer HISR priority to TMD_HISR_Priority */
# TMD_HISR_Priority = TIMER_PRIORITY;
#
li r8,TIMER_PRIORITY # get Timer HISR priority
addis r10,r0,TMD_HISR_Priority@ha # get upper 16 bits and < 16 bits
stw r8,TMD_HISR_Priority@l(r10) # store the Timer HISR priority
#
# /* Add in the Timer HISR stack size to the current system stack size.
# /* Note: This current stack size will now be passed to the INC_Initialize
# routine as the first available memory location for allocating
# system memory blocks. This is why we store it into r3. */
#
addi r1,r1,4 # move to next available
add r1,r1,r9
#
# /* Initialize the MMU */
#
bl MMU_Init
# /* Unlock, invalidate, and enable the caches */
lis r3,CACHE_UNLK_ALL
sync
mtspr DC_CST,r3 # unlock all data cache entries
mtspr IC_CST,r3 # unlock all instr cache entries
lis r3,CACHE_INV_ALL
sync
mtspr DC_CST,r3 # invalidate all data cache entries
mtspr IC_CST,r3 # invalidata all instr cache entries
lis r3,CACHE_ENABLE
sync
mtspr DC_CST,r3 # enable data cache
mtspr IC_CST,r3 # enable instruction cache
isync
# /* Load the DEC register with a value for creating an interrupt
# to the kernel.*/
#
lis r11,DEC_LOAD@h # setup DEC for 10ms periodic
ori r11,r11,DEC_LOAD@l
mtspr DEC,r11 # interrupt
#
# /* Call INC_Initialize with a pointer to the first available memory
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