📄 boot.s
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stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,16 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1100-(.-INT_Vectors) # Instruction TLB miss
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,17 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1200-(.-INT_Vectors) # Data TLB miss
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,18 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1300-(.-INT_Vectors) # Instruction TLB error
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,19 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1400-(.-INT_Vectors) # Data TLB error
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,20 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1C00-(.-INT_Vectors) # Data breakpoint
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,28 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1D00-(.-INT_Vectors) # Instruction breakpoint
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,29 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1E00-(.-INT_Vectors) # Peripheral breakpoint
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,30 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
.skip 0x1F00-(.-INT_Vectors) # Non-maskable development port
addi r1,r1,-8 # subtract 8 bytes for EABI
stw r12,0(r1) # save r12
stwu r11,-4(r1) # save r11
stwu r10,-4(r1) # save r10
stwu r9,-4(r1) # save r9
mfspr r12,SRR0 # read the rfi PC value/SRR0
stwu r12,-4(r1) # save on the stack
li r11,31 # load vector number
mfspr r10,CTR # save CTR temporarily
lis r9,INT_Shell@h
ori r9,r9,INT_Shell@l # load address of INT_Shell
mtspr CTR,r9
bctr # jump to INT_Shell
#
#/*************************************************************************/
#/* */
#/* FUNCTION */
#/* */
#/* INT_Initialize */
#/* */
#/* DESCRIPTION */
#/* */
#/* This function sets up the global system stack variable and */
#/* transfers control to the target independent initialization */
#/* function INC_Initialize. Responsibilities of this function */
#/* include the following: */
#/* */
#/* - Setup necessary processor/system control registers */
#/* - Initialize the vector table */
#/* - Setup the system stack pointers */
#/* - Setup the timer interrupt */
#/* - Calculate the timer HISR stack and priority */
#/* - Calculate the first available memory address */
#/* - Transfer control to INC_Initialize to initialize all of */
#/* the system components. */
#/* */
#/*************************************************************************/
#VOID INT_Initialize(void)
#{
.text
.align 2
INT_Initialize:
li r0,0
#
# /* Disable data cache */
#
lis r3,CACHE_DISABLE
mtspr DC_CST,r3
mtspr IC_CST, r3
# /* Unlock and invalidate the caches */
lis r3,CACHE_UNLK_ALL
sync
mtspr DC_CST,r3 # unlock all data cache entries
mtspr IC_CST,r3 # unlock all instr cache entries
lis r3,CACHE_INV_ALL
sync
mtspr DC_CST,r3 # invalidate all data cache entries
mtspr IC_CST,r3 # invalidata all instr cache entries
#
# /* Enable machine check exceptions and set RI bit */
#
mfmsr r3
ori r3,r3,0x1002
mtmsr r3
#
# /* Set ICTRL = 7 to turn off show cycles */
#
lis r3,0x0000
ori r3,r3,0x0007
mtspr ICTRL,r3
# The flowing set DER added by Zhuguosheng
lis r4,0xFCC7
ori r4,r4,0x400F
sync
mtspr DER,r4
isync
#
# /* Set base address of internal memory-mapped registers */
#
# /* Zhuguosheng should take special attention to the flowing codes. */
# ***** BEGIN board specific code for the FADS board *****
lis r4,0x2200
ori r4,r4,0x0000
mtspr IMMR,r4
#
# ***** END board specific code for the FADS board *****
#
# /* Enable bus monitor, disable SWT */
#
lis r3,0xffff
ori r3,r3,0xff88
stw r3,SYPCR(r4)
#
# /* SIUMCR |= 0x0161,2440 */
#
lwz r3,SIUMCR(r4)
oris r3,r3,0x0161
ori r3,r3,0x2440
stw r3,SIUMCR(r4)
#
# /* Enable decrementer and halt it when FREEZE is asserted */
#
li r3,0x00c3
sth r3,TBSCR(r4)
#
# /* Unlock Real-time clock control register */
#
lis r3,0x55cc
ori r3,r3,0xaa33
stw r3,RTCSCK(r4)
#
# /* Disable real-time clock */
#
li r3,0x00c2
sth r3,RTCSC(r4)
#
# /* Disable periodic timer */
#
li r3,0x0082
sth r3,PISCR(r4)
# /* Set clock to 50MHz. This assumes the board has the 5MHz
# crystal plugged in. */
lis r3,0x55CC
ori r3,r3,0xAA33
stw r3,PLPRCRK(r4) # unlock PLPRCR
lis r3,0x0090 # Set clock to 50MHz.
stw r3,PLPRCR(r4)
lis r3,0x0000
ori r3,r3,0x0000
stw r3,PLPRCRK(r4) # lock PLPRCR
lis r3,0x55CC
ori r3,r3,0xAA33
stw r3,SCCRK(r4) # unlock SCCR
lis r3,0x0182
ori r3,r3,0x0000
stw r3,SCCR(r4)
lis r3,0x0000
ori r3,r3,0x0000
stw r3,SCCRK(r4) # lock SCCR
#
# /* Setup memory controller registers. This code can not be run from
# DRAM when using the debugger. This code should be uncommented only
# when it's being run from Flash */
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