📄 masks860.h
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/* SCC3 Data Synchronization Register (DSR3) */
#define DSR3_SYN2 0xFF00
#define DSR3_SYN1 0x00FF
/* SCC4 */
/* SCC4 General Mode Register (GSMR_L4) */
#define GSMR_L4_SIR 0x80000000 /* Serial Infrared Encoding */
#define GSMR_L4_EDGE 0x60000000 /* Clock Edge */
#define GSMR_L4_TCI 0x10000000 /* Transmit Clock Invert */
#define GSMR_L4_TSNC 0x0C000000 /* Transmit Sense */
#define GSMR_L4_RINV 0x02000000 /* DPLL Receive Input Invert Data */
#define GSMR_L4_TINV 0x01000000 /* DPLL Transmit Input Invert Data */
#define GSMR_L4_TPL 0x00E00000 /* Tx Preamble Length */
#define GSMR_L4_TPP 0x00180000 /* Tx Preamble Pattern */
#define GSMR_L4_TEND 0x00040000 /* Transmitter Frame Ending */
#define GSMR_L4_TDCR 0x00030000 /* Transmit Divide Clock Rate */
#define GSMR_L4_RDCR 0x0000C000 /* Receive DPLL Clock Rate */
#define GSMR_L4_RENC 0x00003800 /* Receiver Decoding Method */
#define GSMR_L4_TENC 0x00000700 /* Transmitter Encoding Method */
#define GSMR_L4_DIAG 0x000000C0 /* Diagnostic Mode */
#define GSMR_L4_ENR 0x00000020 /* Enable Receive */
#define GSMR_L4_ENT 0x00000010 /* Enable Transmit */
#define GSMR_L4_MODE 0x0000000F /* Channel Protocol Mode */
/* SCC4 General Mode Register (GSMR_H4) */
#define RESERVED137 0xFFF80000
#define GSMR_H4_IRP 0x00040000 /* Infrared Rx Polarity */
#define RESERVED138 0x00020000
#define GSMR_H4_GDE 0x00010000 /* Glitch Detect Enable */
#define GSMR_H4_TCRC 0x0000C000 /* Transparent CRC */
#define GSMR_H4_REVD 0x00002000 /* Reverse Data */
#define GSMR_H4_TRX 0x00001000 /* Transparent Receiver */
#define GSMR_H4_TTX 0x00000800 /* Transparent Transmitter */
#define GSMR_H4_CDP 0x00000400 /* CD Pulse */
#define GSMR_H4_CTSP 0x00000200 /* CTS Pulse */
#define GSMR_H4_CDS 0x00000100 /* CD Sampling */
#define GSMR_H4_CTSS 0x00000080 /* CTS Sampling */
#define GSMR_H4_TFL 0x00000040 /* Transmit FIFO Length */
#define GSMR_H4_RFW 0x00000020 /* Rx FIFO Width */
#define GSMR_H4_TXSY 0x00000010 /* Transmitter Synched to Receiver */
#define GSMR_H4_SYNL 0x0000000C /* Sync Length */
#define GSMR_H4_RTSM 0x00000002 /* RTS mode */
#define GSMR_H4_RSYN 0x00000001 /* Receive Sync Timing */
/* SCC4 Transmit_On-Demand Register (TODR4) */
#define TODR4_TOD 0x8000 /* Transmit on Demand */
#define RESERVED139 0x0FFF
/* SCC4 Data Synchronization Register (DSR4) */
#define DSR4_SYN2 0xFF00
#define DSR4_SYN1 0x00FF
/* SI */
/* SI Mode Register (SIMODE) */
#define SIMODE_SMC2 0x80000000 /* SMC2 Connection */
#define SIMODE_SMC2CS 0x70000000 /* SMC2 Clock Source (NMSI mode) */
#define SIMODE_SDMB 0x0C000000 /* SI Diagnostic Mode for TDM B */
#define SIMODE_RFSDB 0x03000000 /* Receive Frame Sync delay TDM B */
#define SIMODE_DSCB 0x00800000 /* Double Speed Clock for TDM B */
#define SIMODE_CRTB 0x00400000 /* Common Rec/Trans Pins for TDM B */
#define SIMODE_STZB 0x00200000 /* Set L1TXDx to Zero for TDM B */
#define SIMODE_CEB 0x00100000 /* Clock Edge for TDM B */
#define SIMODE_FEB 0x00080000 /* Frame Sync Edge for TDM B */
#define SIMODE_GMB 0x00040000 /* Grant Mode for TDM B */
#define SIMODE_TFSDB 0x00030000 /* Transmit Frame Sync Delay TDM B */
#define SIMODE_SMC1 0x00008000 /* SMC1 Connection */
#define SIMODE_SMC1CS 0x00007000 /* SMC1 Clock Source (NMSI mode) */
#define SIMODE_SDMA 0x00000C00 /* SI Diagnostic Mode for TDM A */
#define SIMODE_RFSDA 0x00000300 /* Receive Frame Sync delay TDM A */
#define SIMODE_DSCA 0x00000080 /* Double Speed Clock for TDM A */
#define SIMODE_CRTA 0x00000040 /* Common Rec/Trans Pins for TDM A */
#define SIMODE_STZA 0x00000020 /* Set L1TXDx to Zero for TDM A */
#define SIMODE_CEA 0x00000010 /* Clock Edge for TDM A */
#define SIMODE_FEA 0x00000008 /* Frame Sync Edge for TDM A */
#define SIMODE_GMA 0x00000004 /* Grant Mode for TDM A */
#define SIMODE_TFSDA 0x00000003 /* Transmit Frame Sync Delay TDM A */
/* SI Global Mode Register (SIGMR) */
#define RESERVED161 0xF0
#define SIGMR_ENB 0x08 /* Enable Channel B */
#define SIGMR_ENA 0x04 /* Enable Channel A */
#define SIGMR_RDM 0x03 /* RAM Division Mode */
/* SI Status Register (SISTR) */
#define SISTR_CRORA 0x80 /* Current Route of TDMa Receiver */
#define SISTR_CROTA 0x40 /* Current Route of TDMa Transmitter */
#define SISTR_CRORB 0x20 /* Current Route of TDMb Receiver */
#define SISTR_CROTB 0x10 /* Current Route of TDMb Transmitter */
#define RESERVED162 0x0F
/* SI Command Register (SICMR) */
#define SICMR_CSRRA 0x80 /* Change Shadow RAM for TDM A Receiver */
#define SICMR_CSRTA 0x40 /* Change Shadow RAM for TDM A Transmitter */
#define SICMR_CSRRB 0x20 /* Change Shadow RAM for TDM B Receiver */
#define SICMR_CSRTB 0x10 /* Change Shadow RAM for TDM B Transmitter */
#define RESERVED163 0x0F
/*SI Clock Route Register (SICR) */
#define SICR_GR4 0x80000000 /* Grant Support of SCC4 */
#define SICR_SC4 0x40000000 /* SCC4 Connection */
#define SICR_R4CS 0x38000000 /* Receive Clock Source for SCC4 */
#define SICR_T4CS 0x07000000 /* Transmit Clock Source for SCC4 */
#define SICR_GR3 0x00800000 /* Grant Support of SCC3 */
#define SICR_SC3 0x00400000 /* SCC3 Connection */
#define SICR_R3CS 0x00380000 /* Receive Clock Source for SCC3 */
#define SICR_T3CS 0x00070000 /* Transmit Clock Source for SCC3 */
#define SICR_GR2 0x00008000 /* Grant Support of SCC2 */
#define SICR_SC2 0x00004000 /* SCC2 Connection */
#define SICR_R2CS 0x00003800 /* Receive Clock Source for SCC2 */
#define SICR_T2CS 0x00000700 /* Transmit Clock Source for SCC2 */
#define SICR_GR1 0x00000080 /* Grant Support of SCC1 */
#define SICR_SC1 0x00000040 /* SCC1 Connection */
#define SICR_R1CS 0x00000038 /* Receive Clock Source for SCC1 */
#define SICR_T1CS 0x00000007 /* Transmit Clock Source for SCC1 */
/* Protocol Specific Masks */
/* SCCE Register in HDLC Mode */
#define HDLC_SCCE_RXB 0x0001 /* Complete buffer not received */
#define HDLC_SCCE_TXB 0x0002 /* Last byte of the buffer xmited */
#define HDLC_SCCE_BSY 0x0004 /* frame discarded-no buffer */
#define HDLC_SCCE_RXF 0x0008 /* frame received */
#define HDLC_SCCE_TXE 0x0010 /* some error like CTS lost or overrun */
#define HDLC_SCCE_GRA 0x0080 /* Graceful stop complete */
#define HDLC_SCCE_IDL 0x0100 /* Idle sequence status changed */
#define HDLC_SCCE_FLG 0x0200 /* HDLC idle flag status */
#define HDLC_SCCE_DCC 0x0400 /* DPLL CS Changed */
#define HDLC_SCCE_GLT 0x0800 /* Glitch on Tx */
#define HDLC_SCCE_GLR 0x1000 /* Glitch on Rx */
/* SCCM Register in HDLC Mode */
#define HDLC_SCCM_RXB 0x0001 /* Complete buffer not received */
#define HDLC_SCCM_TXB 0x0002 /* Last byte of the buffer xmited */
#define HDLC_SCCM_BSY 0x0004 /* frame discarded-no buffer */
#define HDLC_SCCM_RXF 0x0008 /* frame received */
#define HDLC_SCCM_TXE 0x0010 /* some error like CTS lost or overrun */
#define HDLC_SCCM_GRA 0x0080 /* Graceful stop complete */
#define HDLC_SCCM_IDL 0x0100 /* Idle sequence status changed */
#define HDLC_SCCM_FLG 0x0200 /* HDLC idle flag status */
#define HDLC_SCCM_DCC 0x0400 /* DPLL CS Changed */
#define HDLC_SCCM_GLT 0x0800 /* Glitch on Tx */
#define HDLC_SCCM_GLR 0x1000 /* Glitch on Rx */
/* PSMR Register in HDLC Mode */
#define HDLC_PSMR_MFF 0x0008 /* Multiple frames in FIFO */
#define HDLC_PSMR_BRM 0x0010 /* HDLC Bus RTS Mode */
#define HDLC_PSMR_BUS 0x0020 /* HDLC Bus Mode */
#define HDLC_PSMR_DRT 0x0040 /* Disable Reciever While Xmitting */
#define HDLC_PSMR_FSE 0x0080 /* Flag Sharing Enable */
#define HDLC_PSMR_RTE 0x0200 /* Retransmit Enable */
#define HDLC_PSMR_16BIT_CRC 0x0000 /* CRC Selection */
#define HDLC_PSMR_32BIT_CRC 0x0800 /* CRC Selection */
#define HDLC_PSMR_NOF_0 0x0000 /* No flags between frames */
#define HDLC_PSMR_NOF_1 0x1000 /* 1 flag between frames */
#define HDLC_PSMR_NOF_2 0x2000 /* 2 flags between frames */
#define HDLC_PSMR_NOF_3 0x3000 /* 3 flags between frames */
#define HDLC_PSMR_NOF_4 0x4000 /* 4 flags between frames */
#define HDLC_PSMR_NOF_5 0x5000 /* 5 flags between frames */
#define HDLC_PSMR_NOF_6 0x6000 /* 6 flags between frames */
#define HDLC_PSMR_NOF_7 0x7000 /* 7 flags between frames */
#define HDLC_PSMR_NOF_8 0x8000 /* 8 flags between frames */
#define HDLC_PSMR_NOF_9 0x9000 /* 9 flags between frames */
#define HDLC_PSMR_NOF_10 0xA000 /* 10 flags between frames */
#define HDLC_PSMR_NOF_11 0xB000 /* 11 flags between frames */
#define HDLC_PSMR_NOF_12 0xC000 /* 12 flags between frames */
#define HDLC_PSMR_NOF_13 0xD000 /* 13 flags between frames */
#define HDLC_PSMR_NOF_14 0xE000 /* 14 flags between frames */
#define HDLC_PSMR_NOF_15 0xF000 /* 15 flags between frames */
/* Transparent Mode */
/* SCCE Register in Transparent Mode */
#define TRAN_SCCE_RXB 0x0001 /* Complete frame not completed */
#define TRAN_SCCE_TXB 0x0002 /* Last byte of the buffer xmited */
#define TRAN_SCCE_BSY 0x0004 /* byte/word discarded-no buffer */
#define TRAN_SCCE_RXH 0x0008 /* byte/word received */
#define TRAN_SCCE_TXE 0x0010 /* some error like CTS lost or overrun */
#define TRAN_SCCE_GRA 0x0080 /* Graceful stop complete */
#define TRAN_SCCE_DCC 0x0400 /* DPLL CS Changed */
#define TRAN_SCCE_GLT 0x0800 /* Glitch on Tx */
#define TRAN_SCCE_GLR 0x1000 /* Glitch on Rx */
/* SCCM Register in Transparent Mode */
#define TRAN_SCCM_RXB 0x0001 /* Complete frame not completed */
#define TRAN_SCCM_TXB 0x0002 /* Last byte of the buffer xmited */
#define TRAN_SCCM_BSY 0x0004 /* byte/word discarded-no buffer */
#define TRAN_SCCM_RXH 0x0008 /* byte/word received */
#define TRAN_SCCM_TXE 0x0010 /* some error like CTS lost or overrun */
#define TRAN_SCCM_GRA 0x0080 /* Graceful stop complete */
#define TRAN_SCCM_DCC 0x0400 /* DPLL CS Changed */
#define TRAN_SCCM_GLT 0x0800 /* Glitch on Tx */
#define TRAN_SCCM_GLR 0x1000 /* Glitch on Rx */
/* Ethernet */
/* SCCE Register in Ethernet Mode */
#define ENET_SCCE_GRA 0x0080; /* Graceful stop Complete */
#define ENET_SCCE_TXE 0x0010; /* Tx Error */
#define ENET_SCCE_RXF 0x0008; /* Rx Frame */
#define ENET_SCCE_BSY 0x0004; /* Busy Condition */
#define ENET_SCCE_TXB 0x0002; /* Tx Buffer */
#define ENET_SCCE_RXB 0x0001; /* Rx Buffer */
/* SCCM Register in Ethernet Mode */
#define ENET_SCCM_GRA 0x0080; /* Graceful stop Complete */
#define ENET_SCCM_TXE 0x0010; /* Tx Error */
#define ENET_SCCM_RXF 0x0008; /* Rx Frame */
#define ENET_SCCM_BSY 0x0004; /* Busy Condition */
#define ENET_SCCM_TXB 0x0002; /* Tx Buffer */
#define ENET_SCCM_RXB 0x0001; /* Rx Buffer */
/* PSMR Register in Ethernet Mode */
#define ENET_PSMR_HBC 0x8000; /* Heartbeat Checking */
#define ENET_PSMR_FC 0x4000; /* Force Collision */
#define ENET_PSMR_RSH 0x2000; /* Receive Short Frames */
#define ENET_PSMR_IAM 0x1000; /* Individual Address Mode */
#define ENET_PSMR_CRC 0x0C00; /* CRC Selection */
#define ENET_PSMR_PRO 0x0200; /* Promiscuous */
#define ENET_PSMR_BRO 0x0100; /* Broadcast Address */
#define ENET_PSMR_SBT 0x0080; /* Stop Backoff Timer */
#define ENET_PSMR_LPB 0x0040; /* Loopback Operation */
#define ENET_PSMR_SIP 0x0020; /* Sample Input Pins */
#define ENET_PSMR_LCW 0x0010; /* Late Collision Window */
#define ENET_PSMR_NIB 0x000E; /* Number of Ignored Bits */
#define ENET_PSMR_FDE 0x0001; /* Full Duplex Ethernet */
/* QMC */
/* SCCE Register in QMC Mode */
#define QMC_SCCE_IQOV 0x0008 /* Interrupt Queue Overflow */
#define QMC_SCCE_GINT 0x0004 /* Global Interrupt */
#define QMC_SCCE_GUN 0x0002 /* Global transmitter Underrun */
#define QMC_SCCE_GOV 0x0001 /* Global Receiver Underrun */
/* SCCM Register in QMC Mode */
#define QMC_SCCM_IQOV 0x0008 /* Interrupt Queue Overflow */
#define QMC_SCCM_GINT 0x0004 /* Global Interrupt */
#define QMC_SCCM_GUN 0x0002 /* Global transmitter Underrun */
#define QMC_SCCM_GOV 0x0001 /* Global Receiver Underrun */
/* QMC Interrupt Table Entry */
#define QMC_ITE_V 0x8000 /* Valid Bit */
#define QMC_ITE_W 0x4000 /* Wrap Bit */
#define QMC_ITE_NID 0x2000 /* Not Idle */
#define QMC_ITE_IDL 0x1000 /* Idle */
#define RESERVED164 0x0800
#define QMC_ITE_CN 0x07C0 /* Channel Number */
#define QMC_ITE_MRF 0x0020 /* Max Rx Frame Length Violation */
#define QMC_ITE_UN 0x0010 /* Tx No Data (Channel Underrun)*/
#define QMC_ITE_RXF 0x0008 /* Rx Frame */
#define QMC_ITE_BSY 0x0004 /* Busy */
#define QMC_ITE_TXB 0x0002 /* Tx Buffer */
#define QMC_ITE_RXB 0x0001 /* Rx Buffer */
#define QMC_ITE_CLEAR 0x0800 /* Use to clear an Interrupt Table
Entry after it has been processed.
Leaves reserved bit intact. */
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